Embedded Solutions Overview

Embedded RISC-V on Lattice: Scalable, Open, and Efficient

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Unlock the power of open-source computing with our embedded RISC-V solution on FPGA. Designed for flexibility, performance, and real time workloads, this platform combines the modularity of RISC-V with the reconfigurability of FPGA technology, ideal for edge devices, industrial automation, and custom SoC development.

Key Features

Open ISA - Graphics
Open ISA

Built on the RISC-V instruction set architecture, enabling royalty-free customization.

Soft-Core Integration
Soft-Core Integration

Supports lightweight cores like RISC-V SM or full-featured RISC-V RX, tailored to your application. 

Peripheral Support with GSRDGHRD
Peripheral Support with GSRD/GHRD

Easily connect UART, SPI, Ethernet, DDR4/DDR5, and more via pre-integrated IP blocks.

Toolchain Compatibility
Toolchain Compatibility

Works with Zephyr, FreeRTOS, Bare Metal, Eclipse IDE, and vendor-specific FPGA tools for streamlined development.

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Ecosystem

Lattice SoC Ecosystem

Lattice SoC Ecosystem - graphics

The Lattice SoC ecosystem is a modular, low-power platform built around RISC-V soft-core processors and a rich set of peripheral IP blocks, designed to accelerate embedded development across industrial, automotive, and edge AI applications. It integrates seamlessly with the Propel Design Environment for drag-and-drop SoC creation, supports popular RTOS like Zephyr and FreeRTOS, and offers secure boot and root-of-trust capabilities via the Sentry stack. With reference designs, training resources, and open-source support, the ecosystem enables rapid prototyping and deployment of scalable, secure, and efficient FPGA-based solutions.

Software Development Tools

To be able to use RISC-V in Lattice FPGA designs, developers rely on Lattice Propel, a powerful and integrated development environment that streamlines both hardware and software design workflows. Propel enables engineers to build custom processor systems based on RISC-V architecture by providing a suite of graphical and command-line tools that simplify the creation, configuration, and debugging of embedded systems. Whether you're designing the hardware architecture using soft IP cores or writing firmware for your application, Propel offers a unified platform that accelerates development, reduces complexity, and ensures compatibility across Lattice’s FPGA families. This makes it an essential tool for implementing open-source RISC-V processors in edge computing, industrial automation, and AI-driven applications.

RISC-V Processor

RISC-V is an open-standard instruction set architecture (ISA) rooted in the principles of Reduced Instruction Set Computing (RISC). Unlike proprietary ISAs such as x86 or ARM, RISC-V is free, open-source, and royalty-free, allowing anyone to design and implement processors without licensing constraints. Its modular and extensible design makes it highly adaptable, from ultra-low-power microcontrollers to high-performance computing systems. With a compact base ISA and optional extensions for features like floating-point, vector processing, and atomic operations, RISC-V offers flexibility and scalability across a wide range of applications. It empowers innovation by eliminating vendor lock-in, fostering a rapidly growing ecosystem of tools, cores, and software. Today, RISC-V is gaining traction globally in embedded systems, edge AI, data centers, and academia, making it a transformative force in the future of computing.

Why RISC-V on FPGA?

  • Customizable Architecture: Modify core features and extensions to suit your workload.
  • Cost-Effective Development: Avoid licensing fees and vendor lock-in.
  • Scalable Performance: From low-power IoT nodes to high-performance compute clusters.
  • Community-Driven: Benefit from a growing ecosystem of open-source tools

IP Cores

IP Category Embedded IP Cores
Processor RISC-V MC CPU
RISC-V RX CPU
RISC-V SM CPU
RISC-V Nano CPU
System Bus / Interconnect AHB-Lite Interconnect Module
AHB-Lite to APB Bridge
AHB-Lite Feedthrough
AHB-Lite to AXI4 Bridge
AHB-Lite Master BFM Lite Version
RISC-V AHB-L I/O Physical Memory Protection (IOPMP)
AXI Register Slice
AXI4 Feedthrough
AXI4 Interconnect
AXI4 Multi Port Bridge for Memory Controller
AXI4 to AHB-Lite Bridge
AXI4 to APB Bridge Module
RISC-V AXI4 I/O Physical Memory Protection (IOPMP)
APB Feedthrough
APB Interconnect
Memory DDR3 SDRAM Controller
DDR4 Memory Controller
LPDDR4 Memory Controller
Embedded & Peripherals Timer/Counter
Watchdog Timer
GPIO
UART
I2C Controller
I2C Target
I3C Controller
I3C Target
I3C Filter
SPI Controller
SPI Target
SPI Flash Memory Controller
Octal SPI Controller
eSPI Target
I/O Interface
Programmable Interrupt Controller
SFB Interface
JTAG Bridge
Mailbox IP
Mutex
DC-SCM LVDS Tunneling Protocol and Interface
QSPI Flash Controller
Scatter-Gather DMA Controller
Internal Flash Controller
System Memory Module
Tightly-Coupled Memory
Networking / Ethernet Tri-speed Ethernet
Ethernet MAC
SGMII and Gb Ethernet PCS
10 Gb Ethernet PCS
10 Gb Ethernet MAC + PHY
2.5 Gb Ethernet MAC + PHY
25 Gb Ethernet MAC + PHY
MDIO Leader
PCIe / JESD / USB PCIE_X1
PCIE_X4
PCIE_X8
JESD204B
USB23
Video & ISP Automatic White Balance
Byte to Pixel Converter
Pixel to Byte Converter
CSI-2/DSI D-PHY Receiver
CSI-2/DSI D-PHY Transmitter
OpenLDI/FPD-Link/LVDS Transmitter
OpenLDI/FPD-Link/LVDS Receiver
SubLVDS Image Sensor Receiver
Video Frame Buffer
Video Scaler
Debayer
Display Interface Multiplexer
MIPI D-PHY to CMOS Interface Bridge
DSP Advanced CNN Accelerator
CNN Co-Processor Accelerator
CNN Plus Accelerator
Coordinate Rotational Digital Computer (CORDIC)
Divider
FFT Compiler
FIR Filter
Security Lattice Sentry Embedded Security Block Mux
Lattice Sentry I2C Filter
Lattice Sentry I2C Monitor
Lattice Sentry QSPI Streamer
Lattice Sentry QSPI Monitor
Lattice Sentry SMBus Mailbox
Lattice Sentry PLD Interface

GHRD/GSRD Reference Design

The Golden System Reference Design (GSRD) is a collection of software and hardware components for developing a wide variety of end-user applications, based on RISC-V RX Processor Core.

The GSRD architecture provides a base level FPGA system design that allows you to add or remove any additional soft-IPs or custom IPs, without having to build the entire FPGA system from scratch

GHRD/GSRD Reference Design and Demo version 1.0 block diagram for Avant-E
GHRD/GSRD Reference Design and Demo version 2.0 block diagram for CertusPro-NX​
GHRD/GSRD Reference Design and Demo version 1.0 block diagram for Certus-NX

Demo

GHRD/GSRD Demonstration

Demo

GHRD/GSRD Demonstration

The Golden Hardware and Software Reference Design comprises of components for developing various kind of applications using CertusPro-NX Versa Board.
GHRD/GSRD Demonstration
MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration

Demo

MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration

This demo illustrates L-ASC10 integration in a MachXO5-NX design and demonstrates RISC-V SOC interfacing with power sequencing and fault response.
MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration
Lattice Sentry Root of Trust Demo for MachXO3D

Demo

Lattice Sentry Root of Trust Demo for MachXO3D

A complete bitstream/firmware package which helps you demonstrate and test a NIST 800-193-compliant PFR solution on the Lattice Sentry Demo Board for MachXO3D
Lattice Sentry Root of Trust Demo for MachXO3D
Multi-Channel Motor Control with Predictive Maintenance Demonstration

Demo

Multi-Channel Motor Control with Predictive Maintenance Demonstration

This design incorporates a RISC-V CPU and processing subsystem supporting multi-channel Motor Control with Predictive Maintenance.
Multi-Channel Motor Control with Predictive Maintenance Demonstration

Kits and Boards

Avant-E Evaluation Board

Board

Avant-E Evaluation Board

The Avant-E Evaluation Board has the ability to expand the usability of the Avant-E FPGA with FMC HPC, PMOD, and Raspberry PI connectors.
Avant-E Evaluation Board
CertusPro-NX Versa Board

Board

CertusPro-NX Versa Board

CertusPro-NX Versa Board supports a wide range industry standards such as MIPI, SFP+, 10 GbE, LPDDR4 and PCIe (Gen3) for rapid prototyping and testing.
CertusPro-NX Versa Board
Secure Connected Motion Control Platform

Board

Secure Connected Motion Control Platform

​​This platform offers resilient connectivity, low power consumption, high performance, and robust security is increasing across various industries.​
Secure Connected Motion Control Platform

Partner Solutions

RISC-V Single Core Linux (SCL) Processor

IP Core

RISC-V Single Core Linux (SCL) Processor

RISC-V Single Core Linux processor includes everything required for running Linux on Lattice FPGAs and supports the RV32IMAC and RV32GC architecture.
RISC-V Single Core Linux (SCL) Processor
SLS I2C Master IP Core

IP Core

SLS I2C Master IP Core

Ease to use I2C Master IP core from SLS. It comes with ready to use HAL driver, reference design and various documents.
SLS I2C Master IP Core
USB 2.0 Device Controller IP Core (USB20SF)

IP Core

USB 2.0 Device Controller IP Core (USB20SF)

USB20SF IP core provides FIFO interface for Data Endpoints while AHB Lite interface for Control Endpoint. This IP core supports High Speed and Full Speed modes
USB 2.0 Device Controller IP Core (USB20SF)
​​USB 2.0 Device IP Core – Software Based Control (USB20SR)​

IP Core

​​USB 2.0 Device IP Core – Software Based Control (USB20SR)​

​USB20SR IP Core is a fully controlled by firmware via AHB-Lite interface. This IP Core supports High Speed, Full Speed and Low Speed functionality as well.​
​​USB 2.0 Device IP Core – Software Based Control (USB20SR)​
​​USB 3.2 Gen 1 Device Controller IP Core (USB32SF)​

IP Core

​​USB 3.2 Gen 1 Device Controller IP Core (USB32SF)​

This IP core solution uses the FPGA’s built-in transceiver for USB 3.2 and ULPI PHY for USB 2.0. It supports SuperSpeed, High Speed and Full Speed modes.
​​USB 3.2 Gen 1 Device Controller IP Core (USB32SF)​
Tachysséma Développement 101 Module

Board

Tachysséma Développement 101 Module

A versatile compact low-power stand-alone module with LPDDR4 & 10G SERDES. Excellent compact solution (27x47m) for embedded imaging and vision applications.
Tachysséma Développement 101 Module
Tachysséma Développement 201 Board

Board

Tachysséma Développement 201 Board

A powerful development board that makes development, testing and validation of FPGA CertusPro-NX projects easier and supports 10 GbE SerDes and LPDDR4 memory.
Tachysséma Développement 201 Board
MAS Educational Board CertusPro-NX

Board

MAS Educational Board CertusPro-NX

Product dedicated to Lattice CertusProâ„¢ -NX, featuring: LPDDR4 x32, Octal SPI 64Mbyte, PCIe x4 Gen 3, PMOD and PMOD+ LVDS, DSI and CSI Onboard Lattice Programmer with USBC and PCIe Power Supply.
MAS Educational Board CertusPro-NX
Lattice Avant G70 PCIe Mini-Board

Board

Lattice Avant G70 PCIe Mini-Board

Avant G70 PCIe Mini-Board with Lattice Avant-G FPGA supports AI, video & industrial use with PCIe, SFP+, FMC, MIPI, memory, clock & more high-performance tasks.
Lattice Avant G70 PCIe Mini-Board
​​tinyCLUNX33 System on Module​

Board

​​tinyCLUNX33 System on Module​

​​1x1" production ready, tightly integrated System on Module using Lattice CrossLinkU-NX (LIFCL-33U) to significantly reduce customers Time to Market.​
​​tinyCLUNX33 System on Module​
UPduino v3.1

Board

UPduino v3.1

The UPDuino v3.1 is a small low-cost board featuring the Lattice iCE40 UltraPlus (ICE40UP5K) and an on-board FPGA programmer, flash, and LED with all FPGA pins.
UPduino v3.1
DPC CCM – Color correction

IP Core

DPC CCM – Color correction

DPC CCM is designed to reduce the difference between the spectral characteristics of an image sensor and the spectral response of the human eye.
DPC CCM – Color correction
DPC Color Conversion

IP Core

DPC Color Conversion

DPC Color Conversion allows real-time conversion of the RGB colour space into the YCbCr colour space.
DPC Color Conversion
DPC Convolution 3x3

IP Core

DPC Convolution 3x3

DPC Conv3x3 applies a kernel to a video stream, in real time, in order to obtain spatial filtering such as Sobel, Gaussian, Laplacian and more.
DPC Convolution 3x3
DPC Debayer

IP Core

DPC Debayer

DPC Debayer reconstructs RGB images, in real time, from RAW data captured by an image sensor.
DPC Debayer
DPC Defective Pixel Correction

IP Core

DPC Defective Pixel Correction

DPC Defective detects and corrects defective pixels in applications with a Bayer pattern image sensor.
DPC Defective Pixel Correction
DPC Gamma RGB

IP Core

DPC Gamma RGB

DPC Gamma RGB is the IP dedicated to correcting, in real time, the gamma transformation curve of an incoming video stream.
DPC Gamma RGB
DPC HDR

IP Core

DPC HDR

DPC HDR obtains an HDR (High Dynamic Range) output stream from two separate input streams (high exposure and low exposure).
DPC HDR
DPC Statistics RGB

IP Core

DPC Statistics RGB

DPC Statistics RGB provides, for each frame, the histograms of the R, G and B channels.
DPC Statistics RGB
DPC Statistics YCbCr

IP Core

DPC Statistics YCbCr

DPC Statistics YCbCr provides, for each frame, the histograms of the Y, Cb and Cr channels.
DPC Statistics YCbCr
DPC Subsampler 4:2:2

IP Core

DPC Subsampler 4:2:2

DPC Subsampler422 is a simple IP block for real-time conversion of a YCbCr 4:4:4 video stream to a YCbCr 4:2:2 stream.
DPC Subsampler 4:2:2
​​PQCryptoLib-Embedded​

Reference Design

​​PQCryptoLib-Embedded​

​PQCryptoLib-Embedded is a versatile, CAVP-compliant version of PQCryptoLib, PQShield’s CMVP-certified library of post-quantum cryptographic algorithms.​
​​PQCryptoLib-Embedded​
​​PQPlatform-SubSys​

IP Core

​​PQPlatform-SubSys​

PQPlatform-SubSys is an autonomous cryptographic subsystem, providing offloaded cryptographic services with minimal integration effort and SCA protection.​
​​PQPlatform-SubSys​
NOEL-V RISC-V Processor IP Core

IP Core

NOEL-V RISC-V Processor IP Core

The NOEL-V is a VHDL model of a processor that implements the RISC-V architecture, which can be configured to conform to the RV32 or RV64 architectures.
NOEL-V RISC-V Processor IP Core
Robust Speaker Identification Model on CrossLink NX-33

Demo

Robust Speaker Identification Model on CrossLink NX-33

An efficient and robust speaker identification model deployed onto the CrossLink-NX-33 Voice and Vision Machine Learning Board with optimized hardware accelerator.
Robust Speaker Identification Model on CrossLink NX-33
IPM-NVMe Device

IP Core

IPM-NVMe Device

The IPM-NVMe_Device IP core designed by IP-Maker is a powerful data transfer manager integrated into the PCIe SSD Controller between the communication interface and the Nandflash controller, therefore off-loading the host CPU.
IPM-NVMe Device

Solution Stacks

Lattice sensAIâ„¢

The Lattice sensAI™ solution stack accelerates the integration of flexible, low power inferencing at the edge. It provides everything needed to evaluate, develop, and deploy FPGA-based machine learning and AI solutions.

Lattice Automateâ„¢

The Lattice Automate™ solution stack enables FPGA-based industrial applications like CNC, robotics, and motor control with predictive maintenance. It also supports real-time networking and cloud connectivity via OPC UA.

Lattice mVisionâ„¢ Solution Stack

The Lattice mVision™ solution stack enables low-power, compact FPGA-based embedded vision applications like robotics, ADAS, and surveillance. It offers modular hardware, IP, and design tools to simplify sensor connectivity, image processing, and interface integration.

Embedded OS

An Embedded Operating System (Embedded OS) is a specialized software layer that manages hardware resources and provides essential services for applications running on embedded systems. These systems are typically designed for specific tasks and operate under strict constraints in terms of power, memory, and performance.

In RISC-V-based embedded designs, the embedded OS plays a critical role in enabling multitasking, hardware abstraction, and real-time responsiveness. Depending on the complexity of the application, developers may choose between:

  • Zephyr RTOS
    A scalable, open-source real-time operating system designed for resource-constrained devices. It supports multitasking, device drivers, and connectivity features ideal for IoT and industrial applications.
  • U-Boot Bootloader
    A flexible and widely used bootloader that initializes hardware and loads the operating system. In RISC-V systems, it operates in machine mode (M-mode) or supervisor mode (S-mode), often working with OpenSBI to manage the boot flow.
  • Bare Metal (Supported by Propel)
    Lattice FPGA Bare-metal HAL driver is the ultimate solution for streamlined hardware interaction in embedded systems. Designed for developers seeking unparalleled control and efficiency, Lattice HAL driver provides a standardized interface for accessing FPGA peripherals without the need for an underlying operating system. It offers optimized functions and data structures for seamless integration into bare-metal environments, ensuring high performance and flexibility, empower applications with direct, low-level access to FPGA hardware resources.
  • FreeRTOS (Supported by Propel)
    A Real-time operating system (RTOS) is an operating system that executes tasks with predictability and determinism. It is designed to execute tasks in a quick and effective manner. RTOS has a small footprint which makes it suitable for embedded systems, particularly for mission or safety critical systems.
    The FreeRTOS open-source project is one of the market leading RTOS available today. Lattice Semiconductor offers FreeRTOS for its RISC-V RX embedded processor.
    The FreeRTOS software, which includes the FreeRTOS kernel and set of libraries are included in Lattice Propel 2022.1 onwards. The FreeRTOS software is distributed under MIT license. Refer to FreeRTOS™ Website for further information.

Documentation

Quick Reference
Technical Resources
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Lattice RISC-V Embedded Design Guidelines
FPGA-AN-02072 1.0 2/25/2024 PDF 1.9 MB
QuestaSim Lattice Edition Usage Guidelines and Tips
FPGA-AN-02053 1.1 2/5/2025 PDF 1.7 MB
Lattice Propel 1.0 API Reference
FPGA-AN-02027 1.0 6/3/2020 PDF 914.5 KB
Lattice CrossLink-NX ISP Demo Quick Start Guide
FPGA-AN-02040 1.0 9/18/2021 PDF 505.8 KB
Scripting Lattice FPGA Build Flow
FPGA-AN-02073 1.0 10/31/2023 PDF 1.2 MB
Composable Custom Extensions on Lattice RISC-V RX User Guide
FPGA-AN-02075 1.1 3/15/2024 PDF 1.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Automate Stack 4.0 Demo - User Guide
FPGA-UG-02231 1.0 3/31/2025 PDF 5.6 MB
FreeRTOS - User Guide
FPGA-IPUG-02225 1.0 4/18/2023 PDF 557.9 KB
Small-sized RISC-V CPU IP Core- Lattice Propel Builder
FPGA-IPUG-02114 1.0 6/3/2020 PDF 1.4 MB
Lattice mVision CSI-2 PCIe Bridge Demo User Guide
FPGA-UG-02125 1.1 3/15/2022 PDF 1.7 MB
RISC-V SM CPU (State Machine) IP Module User Guide - Lattice Propel Builder
FPGA-IPUG-02279 1.0 6/26/2025 PDF 553.8 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Automate Stack 4.0 Reference Design - User Guide
FPGA-RD-02302 1.0 3/31/2025 PDF 4.3 MB
Avant-E Golden System Reference Design and Demo V1.0 - User Guide
FPGA-RD-02296 1.1 12/15/2025 PDF 4.9 MB
CertusPro-NX Golden System Reference Design and Demo V2.0 - User Guide​
FPGA-RD-02300 1.1 12/15/2025 PDF 7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Lattice Propel Product Brochure
IO272 2.0 9/29/2022 PDF 1.8 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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A Step-By-Step Approach to Lattice Propel
FPGA-AN-02052 1.1 2/19/2024 ZIP 6.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Lattice Propel Helps Designers Create Processor-Based Systems in Minutes
WP0029 1.0 2/23/2021 PDF 503.9 KB

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Training Resources

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