System Memory Module

Use of Embedded Block RAMs or Distributed Memory

The System Memory is designed to be fully compatible with the AHB-Lite standard. It can be configured as a single or dual AHB-Lite interface, depending if single or dual port memory is needed. The bridge allows translation of signals from the AHB-L bus into memory compatible signals, which can be directly interpreted by the core memory implementation.

The System Memory Module employs the use of Embedded Block RAMs or Distributed Memory in the MachXO3D family of devices. The memory implementation can be configured as true-dual port, pseudo dual port, single port, or read-only memory.

The IP can be configured and generated using Lattice Propel Builder. It can be targeted to MachXO3D FPGA devices and implemented using the Lattice Diamond Software Place and Route tool integrated with the Synplify Pro synthesis tool.


  • Compliant with AMBA 3 AHB-Lite Protocol v1.0
  • Single or dual port memory (to 1 or 2 AHB-Lite Slave ports)
  • Supports byte writes when used with compatible hardware
  • Supports up to 512 kB maximum memory
  • Uses 32-bit data word transfers and uses little-endian bit structure
Lattice Propel

Block Diagram

System Memory Module Block Diagram


Quick Reference
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System Memory Module - Lattice Propel Builder
FPGA-IPUG-02073 1.2 5/11/2021 PDF 1.6 MB

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