System Memory Module IP Core

Use of Embedded Block RAMs or Distributed Memory

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The System Memory Module is designed to be fully compatible with the AHB-Lite standard. It can be configured as single or dual AHB-Lite interfaces, depending on if single or dual port memory is needed. The signals from the AHB-L bus are translated into memory compatible signals, which can be directly interpreted by the core memory implementation.

Latest Resource Utilization details are available in the IP Core User Guide.

Features

  • Compliant with AMBA 3 AHB-Lite Protocol v1.0
  • Compliant with AMBA AXI4 Protocol
  • Configurable as single or dual port memory, utilizing 1 or 2 AHB-Lite or AXI4 Interfaces
  • Core memory can be implemented as EBR, Distributed RAM, or Large RAM
  • Supports ROM and RAM mode
Lattice Propel

Block Diagram

System Memory Module IP Core Block DiagramExpand Image

Resource Utilization

Avant Family
LAV-AT-500E-2LFG1156C
Configuration Clock Fmax (MHz) Register LUTs EBRs
INTERFACE = AXI4, PORT_COUNT = 1,
MEMORY_TYPE = EBR, ADDR_DEPTH = 8192		 181.324 303 710 8
INTERFACE = AXI4, PORT_COUNT = 2 (R/W + R/W),
MEMORY_TYPE = EBR, ADDR_DEPTH = 8192		 168.039 599 1478 8
INTERFACE = AXI4, PORT_COUNT = 2 (WO + RO),
MEMORY_TYPE = Distributed_RAM, ADDR_DEPTH = 1024,		 148.434 510 5093 8
INTERFACE = AXI4, PORT_COUNT = 1,
MEMORY_TYPE = EBR, ADDR_DEPTH = 8192,
DATA_STREAMER=1, STREAMER_INTF=AXI4 (Stream)		 175.593 364 801 8
INTERFACE = AHBL, PORT_COUNT = 1
MEMORY_TYPE = EBR, ADDR_DEPTH = 8192, 		250 29 131 8
INTERFACE = AHBL, PORT_COUNT = 2 (R/W + R/W)
MEMORY_TYPE = EBR, ADDR_DEPTH = 8192,		 250 58 260 8
INTERFACE = AHBL, PORT_COUNT = 2 (WO + RO)
MEMORY_TYPE = Disributed_RAM, ADDR_DEPTH = 8192,		 232.775 75 4009 8
CertusPro-NX Family
LFCPNX-100-9LFG672C
Configuration Clock Fmax (MHz) Register LUTs EBRs
INTERFACE = AXI4, PORT_COUNT = 1,
MEMORY_TYPE = EBR, ADDR_DEPTH = 8192		 155.812 296 730 16
INTERFACE = AXI4, PORT_COUNT = 2 (R/W + R/W),
MEMORY_TYPE = EBR, ADDR_DEPTH = 8192		 151.286 597 1484 16
INTERFACE = AXI4, PORT_COUNT = 2 (WO + RO),
MEMORY_TYPE = Distributed_RAM, ADDR_DEPTH = 1024		 95.465 530 6589 16
INTERFACE = AXI4, PORT_COUNT = 1,
MEMORY_TYPE = EBR, ADDR_DEPTH = 8192,
DATA_STREAMER=1, STREAMER_INTF=AXI4 (Stream)		 161.865 359 673 16
INTERFACE = AHBL, PORT_COUNT = 1
MEMORY_TYPE = EBR, ADDR_DEPTH = 8192		 200 29 138 16
INTERFACE = AHBL, PORT_COUNT = 2 (W/R + W/R)
MEMORY_TYPE = EBR, ADDR_DEPTH = 8192		 200 58 260 16
INTERFACE = AHBL, PORT_COUNT = 2 (WO + RO)
MEMORY_TYPE = Disributed_RAM, ADDR_DEPTH = 1024		 129.988 74 5444 0

Ordering Information

Available for free to use in Lattice Radiant design software.

 

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
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System Memory Module
FPGA-IPUG-02073 2.2 12/20/2024 PDF 2.9 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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System Memory IP Release Notes
FPGA-RN-02065 1.0 12/20/2024 PDF 324.8 KB

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