The System Memory is designed to be fully compatible with the AHB-Lite standard. It can be configured as a single or dual AHB-Lite interface, depending if single or dual port memory is needed. The bridge allows translation of signals from the AHB-L bus into memory compatible signals, which can be directly interpreted by the core memory implementation.
The System Memory Module employs the use of Embedded Block RAMs or Distributed Memory in the MachXO3D family of devices. The memory implementation can be configured as true-dual port, pseudo dual port, single port, or read-only memory.
The IP can be configured and generated using Lattice Propel Builder. It can be targeted to MachXO3D FPGA devices and implemented using the Lattice Diamond Software Place and Route tool integrated with the Synplify Pro synthesis tool.