Avant-E Family

Optimized for Edge Processing Applications

The Lattice Avant™-E family of mid-range FPGAs are the first products built using the 16nm FinFET Avant platform. This platform has been optimized to deliver the lowest power, smallest form factor, and highest performance FPGA devices in their class. The Avant-E family delivers the highest DSP and embedded memory to logic ratio for mid-range FPGAs, enabling intelligence at the edge for applications in automotive, communications, compute, and industrial market segments.

High Performance, Compact, and low power – High logic capacity from 200k to 500k LCs, smallest 11 x 9 mm package option, and up to 2.5x lower power than competition

Fast External Memory Support - LPDDR4/DDR4 at 1800 Mbps

Efficient Edge AI Processing – Up to 7200 INT8 multipliers and 36 Mb embedded memory enable more efficient implementation of AI/ML algorithms

Lattice will introduce additional Avant families to leverage the full capabilities of the platform. Click here to be notified as new devices become available.

Features

  • Up to 500k Logic Cells, 36 Mb of embedded memory and 1800 - 18x18 multipliers (7200 - 8x8 multipliers)
  • Lowest power: Up to 2.5x lower power than competitive FPGAs in similar density
  • Packages as small as 11x9 mm (200k LCs) or 15x13 mm (500k LCs)
  • AI optimized DSP block enables 18x18 multipliers that can be split into four 8x8 multipliers
  • Fast configuration: I/O configures in 10ms, and full configuration for 500k LC in 60 ms
  • Available in Commercial and Industrial Grades

Jump to

Avant-E Family Selection Guide
Features Avant-AT-200E Avant-AT-300E Avant-AT-500E
Logic Cells 196k 306k 477k
Embedded Memory (EBR) Blocks (36 kb) 400 630 990
Embedded Memory (Mb) 14.4 22.7 35.6
Distributed RAM Bits (kb) 1700 2660 4140
DSP (18x18 Multipliers) 700 1120 1800
DSP (8x8 Multipliers)1 2800
4480 7200
High Frequency Oscillator (400 MHz) 1 1 1
GPLL (WRPLL, HPPLL) 1,5 2,7 2,9
External Memory Interface support LPDDR4/DDR4 LPDDR4/DDR4 LPDDR4/DDR4
Temperature Grades2 C, I C, I C, I
0.5 mm Total I/O (Wide Range, High Performance)
  Avant-AT-200E Avant-AT-300E Avant-AT-500E
ASG324 (11 x 9 mm) WLCSP
208 (52,156) - -
CSG484 (12 x 12 mm) FCCSP
- 230 (52,178) -
CSG676 (15 x 13 mm) FCCSP
- - 312 (52,260)
0.8 mm Total I/O (Wide Range, High Performance)
  Avant-AT-200E Avant-AT-300E Avant-AT-500E
LBG484 (19 x 19 mm) FCBGA
230 (52,178) 230 (52,178) -
1.0 mm Total I/O (Wide Range, High Performance)
  Avant-AT-200E Avant-AT-300E Avant-AT-500E
LFG676 (27 x 27 mm) FCBGA
312 (52,60) 312 (52,60) 312 (52,60)
LFG1156 (35 x 35 mm) FCBGA
- 468 (104,364) 572 (104,468)

1. One 18x18 multiplier fractures into four 8x8 multipliers
2. C=Commercial, I=Industrial

Example Use Cases

Industrial Switch / Gateway

  • Flexible Industrial Ethernet and Field Bus Interfaces
  • RISC-V CPU and Lattice Propel System Design Tools HW
  • Low Latency, deterministic switching and control processing, protocol acceleration

IP Network Camera

  • Sensor Interface - MIPI, LVDS
  • Customizable ISP for image processing
  • Lattice sensAI Artificial Intelligence for object/defect detection
  • JPEG-XS compression enables lossless low latency streaming over Gigabit IP Networks

Robot Vision and Control

  • Multi-channel Camera / sensor bridging and aggregation
  • Multi-channel Camera / sensor pre-processing and synchronization
  • Real time sync, sense & control, multi-axis
  • Internal Soft CPU and/or External CPU

Smart IP Network Camera

  • IP Network, GigE Vision output
  • MIPI, LVDS sensor interface and control
  • Image Signal Processing
  • Computer Vision / AI / ML processing
  • Optional Lossless Compression – reduce BW 10X
  • Streaming over IP networks

Zonal Controller / Gateway for Centralized Compute Architectures

  • Ultra-low latency HW-optimized routing
  • Flexible Ethernet and sensor / actuator port configurations
  • Flexible video & image resolution and interface support
  • Optional low latency, lossless compression to optimize Camera transmission bandwidth requirements
  • Integrated state of the art HW accelerated security engine

Videos

Lattice Avant™ FPGA Platform: Power Efficiency Demo

Lattice Avant™ FPGA Platform: Power Efficiency Demo

Watch how the Lattice Avant FPGA platform delivers up to 2.5X lower power than similar class competitive devices, helping system and application engineers achieve power efficiency while simplifying thermal management and lowering operating costs.
Lattice Avant™ FPGA Platform: AI Processing Demo

Lattice Avant™ FPGA Platform: AI Processing Demo

Watch how the Lattice Avant FPGA platform provides scalable AI performance for Automotive applications. Lattice Avant FPGAs are designed to solve key customer challenges at the Edge by combining class-leading power efficiency, size and performance with an optimized feature set tailored to the needs of Edge applications like data processing and AI.

Design Resources

開発キット&ボード

当社の開発キットとボードで設計プロセスの合理化

IP & リファレンスデザイン

事前検証済み、開発期間を短縮

開発ソフトウェア

使いやすく、開発に必要な機能を提供

Documentation

Quick Reference
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
[IBIS AMI] LAV-AT
This document would be provided through Technical Support Request after sign-in to the Lattice web site. Please refer to Answer Database FAQ 6539 for detailed instructions.
FPGA-MD-02041 0.80 12/5/2022 WEB
Lattice Avant-E Delphi Models
FPGA-MD-02038 0.80 12/5/2022 ZIP 1.8 KB
Lattice Avant Platform - Overview Data Sheet
FPGA-DS-02107 0.71 12/5/2022 PDF 1.6 MB
Package Diagrams
FPGA-DS-02053 7.2 12/14/2022 PDF 9.7 MB
Lattice Avant-E Pinout
FPGA-SC-02037 0.80 12/5/2022 CSV 49.1 KB
[IBIS] LAV-AT
FPGA-MD-02039 0.81 12/5/2022 ZIP 2 MB
Lattice Avant Multi-Boot User Guide
FPGA-TN-02314 0.80 12/5/2022 PDF 398 KB
Lattice Avant Hardware Checklist
FPGA-TN-02317 0.80 12/5/2022 PDF 910.4 KB
Lattice Avant sysCONFIG User Guide
FPGA-TN-02299 0.83 12/15/2022 PDF 2.2 MB
Lattice Avant sysCLOCK PLL Design and User Guide
FPGA-TN-02298 0.82 12/5/2022 PDF 1.7 MB
Lattice Avant sysI/O User Guide
FPGA-TN-02297 0.80 12/5/2022 PDF 573.2 KB
Lattice Avant sysDSP User Guide
FPGA-TN-02293 0.81 12/5/2022 PDF 1.6 MB
Lattice Avant High-Speed I/O and External Memory Interface User Guide
FPGA-TN-02300 0.81 12/5/2022 PDF 1.9 MB
Lattice Avant Embedded Memory User Guide
FPGA-TN-02289 0.81 12/5/2022 PDF 2.2 MB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 2.3 12/5/2022 PDF 1.2 MB
Reflow Temperature Guidelines and Moisture Sensitivity
FPGA-TN-02041 4.7 12/5/2022 PDF 812.2 KB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 5.1 12/5/2022 PDF 6.2 MB
Thermal Management
FPGA-TN-02044 4.4 12/5/2022 PDF 1.1 MB
Using TraceID
FPGA-TN-02084 2.5 1/25/2023 PDF 400.6 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Lattice Avant Platform - Overview Data Sheet
FPGA-DS-02107 0.71 12/5/2022 PDF 1.6 MB
Lattice Avant Platform - Specifications Data Sheet
FPGA-DS-02112 0.71 12/5/2022 PDF 1.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Lattice Avant Multi-Boot User Guide
FPGA-TN-02314 0.80 12/5/2022 PDF 398 KB
Lattice Avant Hardware Checklist
FPGA-TN-02317 0.80 12/5/2022 PDF 910.4 KB
Lattice Avant sysCONFIG User Guide
FPGA-TN-02299 0.83 12/15/2022 PDF 2.2 MB
Lattice Avant sysCLOCK PLL Design and User Guide
FPGA-TN-02298 0.82 12/5/2022 PDF 1.7 MB
Lattice Avant sysI/O User Guide
FPGA-TN-02297 0.80 12/5/2022 PDF 573.2 KB
Lattice Avant sysDSP User Guide
FPGA-TN-02293 0.81 12/5/2022 PDF 1.6 MB
Lattice Avant High-Speed I/O and External Memory Interface User Guide
FPGA-TN-02300 0.81 12/5/2022 PDF 1.9 MB
Lattice Avant Embedded Memory User Guide
FPGA-TN-02289 0.81 12/5/2022 PDF 2.2 MB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 2.3 12/5/2022 PDF 1.2 MB
Reflow Temperature Guidelines and Moisture Sensitivity
FPGA-TN-02041 4.7 12/5/2022 PDF 812.2 KB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 5.1 12/5/2022 PDF 6.2 MB
Thermal Management
FPGA-TN-02044 4.4 12/5/2022 PDF 1.1 MB
Using TraceID
FPGA-TN-02084 2.5 1/25/2023 PDF 400.6 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Package Diagrams
FPGA-DS-02053 7.2 12/14/2022 PDF 9.7 MB
Lattice Avant-E Pinout
FPGA-SC-02037 0.80 12/5/2022 CSV 49.1 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Introducing the Lattice Avant™ Platform: Designed for the Mid-Range
1.0 12/5/2022 PDF 539.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Lattice Avant-E Delphi Models
FPGA-MD-02038 0.80 12/5/2022 ZIP 1.8 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
[IBIS AMI] LAV-AT
This document would be provided through Technical Support Request after sign-in to the Lattice web site. Please refer to Answer Database FAQ 6539 for detailed instructions.
FPGA-MD-02041 0.80 12/5/2022 WEB
[IBIS] LAV-AT
FPGA-MD-02039 0.81 12/5/2022 ZIP 2 MB

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