Guidance Systems

Meet mission requirements with low power and high reliability advantages of Lattice FPGAs

For over 25 years, , Lattice has enabled leading-edge guidance systems with a wide range of high reliability, SWAP-C optimized products that meet today’s security, longevity, and extreme environment challenges. Engineers at leading defense contractors rely on our deep system-level knowledge, collaborative spirit, local support, and design resources to meet the most stringent design requirements.

Lattice COTS FPGAs provide the flexibility to adapt to the requirements of next generation precision guided systems with low power actuator control, sensor fusion, and signal processing solutions. The latest Lattice Nexus platform features industry leading low power and high reliability to meet the challenging requirements of next generation guidance platforms.

Key Lattice FPGA Features & Benefits

  • Superior low power consumption and thermal performance compared to other FPGAs, enabling longer missions, and simplifying thermal management
  • Industry leading small form factor FPGAs, optimized for highest I/O density, connect to more sensors, creating a high-fidelity situational awareness
  • Lowest soft error rate (SER) in its class and highest latch-up immunity to maximize integrity of ground-based and airborne systems
  • Enables low latency, deterministic, instant-on start-up with initial I/O configuration in less than 3 ms and full device configuration in as little as 8 ms

Jump to

Example Applications

Actuator Control

  • Single-chip non-volatile FPGAs with 2ms bitstream verification, authentication and boot-up time
  • Embedded A/D converters for sensor fusion, feedback and sensing
  • Packages as small as 6x6 mm, and in ball-pitch options of 0.5 and 0.8 mm

Trigger

  • Critical bitstream verification and safety compliance
  • ECDSA bitstream authentication, coupled with robust AES-256 encryption
  • Robust flash-based FPGAs ideal for sensor processing and control

Telemetry

  • Power efficient, highly reliable system control and monitoring
  • Optimum integration level with embedded MCU and ADCs
  • Utmost control and flexibility in sense and control of rea-time data

Reference Designs

SPIスレーブからPWM生成

Reference Design

SPIスレーブからPWM生成

Sets the frequency and duty cycle of a PWM (Pulse-Width Modulator) using data from an external SPI master.
SPIスレーブからPWM生成
簡易シグマデルタ ADC

Reference Design

簡易シグマデルタ ADC

Implements an Analog-to-Digital (ADC) using on-FPGA differntial LVDS inputs (or inexpensive analog comparitor). Save cost by eliminating external ADC devices.
簡易シグマデルタ ADC
組込み機能ブロックを使ったI2Cスレーブ周辺機器

Reference Design

組込み機能ブロックを使ったI2Cスレーブ周辺機器

Ready to use RTL code segment that implements intuitive interface between an external I2C master and the MachXO2 internal registers or memory extension in XO2
組込み機能ブロックを使ったI2Cスレーブ周辺機器
ADC インターフェース

Reference Design

ADC インターフェース

Interfaces with the Texas Instruments (TI) ADS64XX family of ADCs via LatticeECP3 FPGA high-speed LVDS I/O
ADC インターフェース

IP Cores

ピクセル - バイト変換

IP Core

UART 16550 IP コア

IP Core

UART 16550 IP コア

設定可能な UART ポート。PC16550D に準拠。7 または 8 ビットデータ幅、TX 用 1、1.5、2 ストップビット、マルチパリティ、ボーレートオプション
UART 16550 IP コア
PCI Express x1, x4 Root Complex Lite IP Core

IP Core

PCI Express x1, x4 Root Complex Lite IP Core

Provides a x1 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCIe protocol stack
PCI Express x1, x4 Root Complex Lite IP Core

Development Kits & Boards

ECP5 Versa 開発キット

Board

ECP5 Versa 開発キット

ECP5 Versa開発キットでPCI Express,、Gigabit Ethernet、DDR3、汎用Serdesパフォーマンスを含むECP5の主要機能の迅速な評価が可能
ECP5 Versa 開発キット
ECP5-5G Versa開発キット

Board

ECP5-5G Versa開発キット

PCI Express、Gigabit Ethernet、DDR3、ECP5-5G SERDESの性能を評価する
L-ASC10ブレークアウトボード

Board

L-ASC10ブレークアウトボード

L-ASC10デバイスを評価および設計する多才なハードウェアプラットフォームです。 このボードは、プラットフォームマネージャー 2開発キットとともに動作するように設計されています。
L-ASC10ブレークアウトボード
POWR1014A Breakout Board

Board

POWR1014A Breakout Board

A simple low-cost board that provides complete I/O access to the Power Manager II (POWR1014A)+LEDs, Prototyping area and more.
POWR1014A Breakout Board

Demos

Power Sequencing with Fault Logging Demo

Demo

Power Sequencing with Fault Logging Demo

Uses L-ASC10 to monitor, sequence four separate Power Planes from a central control point. Logs faults with timestamps. Expandable.
Power Sequencing with Fault Logging Demo

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Soft Error Detection (SED)/Correction (SEC) Usage Guide for Nexus Platform
FPGA-TN-02076 1.1 6/24/2020 PDF 1005.1 KB
Multi-Boot Usage Guide for Nexus Platform
FPGA-TN-02145 1.1 5/31/2020 PDF 1.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Soft Error Detection (SED)/Correction (SEC) Usage Guide for Nexus Platform
FPGA-TN-02076 1.1 6/24/2020 PDF 1005.1 KB
Multi-Boot Usage Guide for Nexus Platform
FPGA-TN-02145 1.1 5/31/2020 PDF 1.2 MB
Implementing JOTP-051-Compliant Safety Features in Lattice FPGAs
FPGA-TN-02150 1.0 9/30/2020 PDF 651.2 KB

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