FIR Filter Generator IP Core

Widely Configurable, Multi-channel FIR Filters

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The Lattice Finite Impulse Response (FIR) Filter IP Core is implemented using high performance Digital Signal Processing (DSP) blocks available in Lattice devices. The input data, coefficient, and output data widths are configurable over a wide range. The IP core uses full internal precision while allowing variable output precision with several choices for saturation and rounding. The coefficients of the filter can be specified at generation time and/or reloadable during run-time through input ports.

Resource Utilization details are available in the IP Core User Guide.

Features

  • Variable number of taps up to 1024
  • Input data and coefficient widths of 4 to 16 bits
  • Multi-channel support for up to 64 channels
  • Signed or unsigned input data and coefficients
  • Coefficients symmetry and negative symmetry optimization

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Block Diagram

FIR Filter Block DiagramExpand Image

FIR Filter IP Core Functional Diagram

Resource Utilization

IP Configuration for Nexus Family
LFMXO5-25-9BBG400I
Configuration Clk Fmax (MHz)1 Registers LUTs EBRs DSPs
Default 200 60 12 0 16
Reloadable Coefficients: true,
Reorder Coefficients Inside: true,
Others = Default		 200 650 32 0 16
Input Data Width: 18,
Precision Control (Overflow): Wraparound,
Precision Control (Rounding): Rounding up,
Others = Default		 200 66 12 0 16
Synchronous Reset: true,
Clock Enable: true,
Others = Default		 200 62 66 0 16
Data Memory Type: Distributed,
Coefficients Memory Type: Distributed,
Output Buffer Type: Distributed,
Others = Default		 200 60 12 0 16

1. Fmax is generated when the FPGA design only contains FIR Filter IP Core, and the target frequency is 200MHz. These values may be reduced when user logic is added to the FPGA design..

LFMXO5-25-7BBG400I
Configuration Clk Fmax (MHz)1 Registers LUTs EBRs DSPs
Default 200 60 12 0 16
Reloadable Coefficients: true,
Reorder Coefficients Inside: true,
Others = Default		 191 650 34 0 16
Input Data Width: 18,
Precision Control (Overflow): Wraparound,
Precision Control (Rounding): Rounding up,
Others = Default		 190 66 12 0 16
Synchronous Reset: true,
Clock Enable: true,
Others = Default		 188 62 66 0 16
Data Memory Type: Distributed,
Coefficients Memory Type: Distributed,
Output Buffer Type: Distributed,
Others = Default		 200 60 12 0 16

1. Fmax is generated when the FPGA design only contains FIR Filter IP Core, and the target frequency is 200MHz. These values may be reduced when user logic is added to the FPGA design.

ECP51
Mode SLICEs LUTs Registers DSP Slices sysMEM EBRs fMAX (MHz)
4 channels, 64 taps, multiplier multiplexing 64 129 248 222 4 2 211
1 channel, 32 taps, multiplier multiplexing 1 80 151 148 32 - 264
1 channel, 32 taps, multiplier multiplexing 4 260 239 482 10 8 177

1. Performance and utilization characteristics are generated targeting LFE5UM-85F-8BG756I using Lattice Diamond 3.10.2 and Synplify Pro F-2013.09L beta software. When using this IP core in a different density, speed, or grade within the ECP5 device family or in a different software version, performance may vary.

LatticeECP31
Mode SLICEs LUTs Registers DSP Slices sysMEM EBRs fMAX (MHz)
4 channels, 64 taps, multiplier multiplexing 64 134 254 222 4 2 277
1 channel, 32 taps, multiplier multiplexing 1 84 155 148 32 - 207
1 channel, 32 taps, multiplier multiplexing 4 260 268 482 10 8 153

1. Performance and utilization characteristics are generated targeting an LFE3-150EA-6FN672C device using Lattice Diamond 3.10.2 and Synplify Pro D-2013.09L beta software. Performance may vary when using this IP core in a different density, speed or grade within the LatticeECP3 family or in a different software version.

To view the complete Resource Utilization of the FIR Filter Generator IP Core, click here to view the table.

Ordering Information

Device Family Part Number
Multi-site Perpetual Single Machine Annual
Certus-N2 FIR-COMP-CN2-UT FIR-COMP-CN2-US
Avant-G FIR-COMP-AVG-UT FIR-COMP-AVG-US
Avant-X FIR-COMP-AVX-UT FIR-COMP-AVX-US
Avant-E FIR-COMP-AVE-UT FIR-COMP-AVE-US
MachXO5-NX FIR-COMP-XO5-UT FIR-COMP-XO5-US
CertusPro-NX FIR-COMP-CPNX-UT FIR-COMP-CPNX-US
CrossLink-NX FIR-COMP-CNX-UT FIR-COMP-CNX-US
Certus-NX FIR-COMP-CTNX-UT FIR-COMP-CTNX-US
ECP5 FIR-COMP-E5-UT FIR-COMP-E5-US
LatticeECP3 FIR-COMP-E3-UT4 FIR-COMP-E3-US
LatticeECP2M FIR-COMP-PM-UT4 -
LatticeECP2 FIR-COMP-P2-UT4 -
LatticeEC/ECP FIR-COMP-E2-UT4 -
LatticeXP2 FIR-COMP-X2-UT4 -
Bundled DSP-BNDL-UT DSP-BNDL-US

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the FIR Filter Generator IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
FIR Filter IP User Guide
FPGA-IPUG-02095 1.4 12/20/2024 PDF 780.2 KB
FIR Filter IP Core
FPGA-IPUG-02043 1.6 6/30/2021 PDF 1.5 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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FIR Filter IP Release Notes
FPGA-RN-02025 1.0 12/20/2024 PDF 211.3 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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The FPGA as a Flexible and Low-Cost Digital Solution for Wireless Base Stations
3/1/2007 PDF 384.9 KB
5G OFDM Modulation with Lattice iFFT and FIR IPs Use Case
WP0042 3/25/2025 PDF 3.8 MB

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