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Lattice OCP Ready Solutions for DC-SCM and HPM CPLD Connectivity

Empowering Interoperable, Scalable, and Low-Power Server Management

Lattice Semiconductor offers cutting-edge IP cores and reference designs—LTPI (LVDS Tunneling Protocol & Interface) and MPESTI (Modular Peripheral Sideband Tunneling Interface)—that are fully compliant with OCP DC-SCM 2.0/2.1 specifications, enabling seamless connectivity between Secure Control Modules (SCM) and Host Processor Modules (HPM).

OCP-solution-provider-logo-color-vert-3x-v2-5 

Key Features

OCP Compliant - Graphics
OCP Compliant
Aligns with DC-SCM 2.0/2.1 standards

Modular Scalable - Graphics
Modular & Scalable
Enables flexible, optimized resource; server design and upgrades

Secure & Resilient - Graphics
Secure & Resilient
Root of Trust (RoT) implementations

Validated Ecosystem - Graphics
Validated Ecosystem
Proven interoperability with major server vendors

Jump to

Block Diagram

LPTI BD放大图片

DC-SCM 2.0 LVDS Tunneling Protocol & Interface (LTPI) Block Diagram

Videos

OCP Overview - Video Thumbnail

OCP Overview

LVDS Tunneling Protocol & Interface (LTPI) Reference Design Walkthrough-Thumbnail

LVDS Tunneling Protocol & Interface (LTPI) Reference Design Walkthrough Guide

LVDS Tunneling Protocol & Interface (LTPI) IP Walkthrough-Thumbnail

LVDS Tunneling Protocol & Interface (LTPI) IP Walkthrough

Virtual Laboratory for Remote Demonstration-Thumbnail

Virtual Laboratory for Remote Demonstration

Dual Host Processor Module HPM and Single Secure Control Module SCM Proof of Concept Demo - Thumbnail

Dual Host Processor Module (HPM) and Single Secure Control Module (SCM) Proof of Concept Demo

Device Attestation over LVDS Tunneling Protocol & Interface Specification (LTPI) - Thumbnail

Device Attestation over LVDS Tunneling Protocol & Interface Specification (LTPI)

Intel Lincoln City Reference Architecture with Lattice FPGAs-Thumbnail

Intel Lincoln City Reference Architecture with Lattice FPGAs

IP Cores

​​eSPI Target IP核​

IP Core

​​eSPI Target IP核​

莱迪思eSPI Target IP核符合英特尔eSPI规范，且在用户界面中拥有自己的虚拟线通道。
MachXO5-NX, Mach-NX, MachXO3D, MachXO3, MachXO2  
APB, AHB-Lite, Lattice Sentry, OCP 
​​eSPI Target IP核​
​​M-PESTI Initiator IP核

IP Core

​​M-PESTI Initiator IP核

莱迪思M-PESTI IP核可在系统启动前检测外设存在和属性采集。
Certus-N2, Avant-G, Avant-X, Avant-E, MachXO5-NX, MachXO3D, MachXO3, Mach-NX 
MPESTI, UART, APB, Lattice Sentry, OCP 
​​M-PESTI Initiator IP核
DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core

IP Core

DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core

LTPI IP Core is an Open Computer Project Data Center – Secure Control Module Standards compatible solution which is introduced in the DC-SCM 2.0 Specification.
CertusPro-NX, CrossLink-NX, Certus-NX, MachXO3, MachXO3D, MachXO5-NX, Mach-NX 
CRC, LVDS, LTPI, AMBA, APB, Lattice Diamond, Lattice Radiant, Lattice Sentry, OCP 
DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core

Reference Designs

Lattice Sentry 4.0 SCM和HPM CPLD参考设计

Reference Design

Lattice Sentry 4.0 SCM和HPM CPLD参考设计

这是一个Sentry 4.0服务器解决方案平台的安全控制模块（SCM）和主机平台模块（HPM）的CPLD设计模板。
MachXO3D, MachXO5-NX 
SCM, HPM, CPLD, Lattice Sentry, Security, Defense, LTPI, MPESTI, SGPIO, eSPI, OCP 
Lattice Sentry 4.0 SCM和HPM CPLD参考设计
MPESTI Initiator Reference Design

Reference Design

MPESTI Initiator Reference Design

MPESTI Initiator Reference Design provides the solution template which is compliant with the MPESTI Base Specification.
Avant-E, MachXO5-NX, MachXO3, MachXO3D 
MPESTI, UART, APB, AHB, RISC-V, OCP 
MPESTI Initiator Reference Design
LVDS Tunneling Protocol and Interface Reference Design

Reference Design

LVDS Tunneling Protocol and Interface Reference Design

The DC-SCM 2.0 LTPI Reference Design provides multiple solution compliant with DC-SCM 2.0 with a standardized DC-SCI and aggregating multiple data channels.
MachXO5-NX, MachXO3D, MachXO3, Mach-NX 
CRC, LVDS, I2C, GPIO, UART, LTPI, AMBA, APB, Lattice Diamond, Lattice Propel, OCP 
LVDS Tunneling Protocol and Interface Reference Design

Documentation

快速参考
技术资源
标题 编号 版本 日期 格式 文件大小
选择全部
LTPI Hardware Checklist
FPGA-TN-02417 1.0 10/7/2025 PDF 521.6 KB
LTPI Quick Start Guide
FPGA-AN-02108 1.0 10/7/2025 PDF 1 MB
标题 编号 版本 日期 格式 文件大小
选择全部
DC-SCM LTPI IP Core – User Guide
FPGA-IPUG-02200 2.0 10/13/2025 PDF 2.1 MB
eSPI Target IP – User Guide
FPGA-IPUG-02260 1.1 12/20/2024 PDF 1.4 MB
M-PESTI Initiator IP Core – User Guide
FPGA-IPUG-02258 1.3 7/15/2025 PDF 1.5 MB
标题 编号 版本 日期 格式 文件大小
选择全部
Lattice Sentry 4.0 SCM and HPM CPLD Reference Design – Source Code
9/5/2024 ZIP 86 MB
LVDS Tunneling Protocol and Interface Reference Design – Source Code
10/27/2025 ZIP 247.8 MB
LVDS Tunneling Protocol and Interface Reference Design – User Guide
FPGA-RD-02247 1.5 10/27/2025 PDF 3.5 MB
MPESTI Initiator Reference Design – Source Code
4/4/2025 ZIP 15.7 MB
MPESTI Initiator Reference Design – User Guide
FPGA-RD-02312 1.0 4/4/2025 PDF 2.9 MB
MachXO3D Lattice Sentry 4.0 SCM and HPM CPLD Reference Design – User Guide
FPGA-UG-02222 1.0 10/28/2025 PDF 4.9 MB

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