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  • AHB-Lite Manager Bus Functional Model (BFM) VIP Core

    IP Core

    AHB-Lite Manager Bus Functional Model (BFM) VIP Core

    Lattice AHB-Lite Manager BFM Lite VIP enables configurable AHB-Lite transaction generation for verification and simulation.
  • USB 2.0/3.2 IP Core

    IP Core

    USB 2.0/3.2 IP Core

    Lattice USB 2.0/3.2 IP Core provides a solution to interface with a USB host and can be targeted to the Lattice CrossLink-NX FPGA Devices.
    USB 2.0/3.2 IP Core
  • ​​eSPI Target IP Core​

    IP Core

    ​​eSPI Target IP Core​

    ​​Lattice eSPI Target IP Core is compliant with the Intel eSPI specifications & has its own virtual wire channel in the user interface.​
    ​​eSPI Target IP Core​
  • PCI Express for Nexus FPGAs

    IP Core

    PCI Express for Nexus FPGAs

    The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express for Nexus FPGAs
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
    RISC-V MC CPU IP Core
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • RISC-V RX CPU IP Core

    IP Core

    RISC-V RX CPU IP Core

    Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.
    RISC-V RX CPU IP Core
  • PCI Express for Avant and Nexus 2 FPGAs

    IP Core

    PCI Express for Avant and Nexus 2 FPGAs

    The Lattice PCIe X8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express for Avant and Nexus 2 FPGAs
  • RISC-V Nano CPU IP Core

    IP Core

    RISC-V Nano CPU IP Core

    The RISC-V Nano CPU IP contains a 32-bit RISC-V processor core that supports the RV32I instruction set and a lightweight interrupt merge controller.
    RISC-V Nano CPU IP Core
  • Lattice Sentry PLD Interface IP Core

    IP Core

    Lattice Sentry PLD Interface IP Core

    Lattice Semiconductor Customer Programmable Logic Devices (PLD)implements a bidirectional mailbox for sending and receiving messages.
    Lattice Sentry PLD Interface IP Core
  • PIC IP Core

    IP Core

    PIC IP Core

    Lattice Semiconductor PIC soft IP with configurable 1~8 interrupt inputs and 32-bit AHB-L interface for Mach-NX FPGA
    PIC IP Core
  • SFB Interface IP Core

    IP Core

    SFB Interface IP Core

    SFB allow access to AHB-L CPLD block , management CPU recovery circuit and Flash sector for read/write.
    SFB Interface IP Core
  • Lattice Sentry I2C Filter IP Core

    IP Core

    Lattice Sentry I2C Filter IP Core

    Sentry I2C Filter IP Core provides an interface between I2C bus devices and a host processor while protecting against common I2C bus vulnerabilities.
    Lattice Sentry I2C Filter IP Core
  • AXI4 to AHB-Lite Bridge Module IP Core

    IP Core

    AXI4 to AHB-Lite Bridge Module IP Core

    Lattice Semiconductor AXI4 to AHB-Lite Bridge Module provides an interface between the high-speed AXI4 and AHB-Lite.
    AXI4 to AHB-Lite Bridge Module IP Core
  • AHB-Lite to AXI4 Bridge Module IP Core

    IP Core

    AHB-Lite to AXI4 Bridge Module IP Core

    The Lattice AHB-Lite to AXI4 Bridge IP Core is used for interfacing one AHB-Lite Manager and one AXI4 Subordinate.
    AHB-Lite to AXI4 Bridge Module IP Core
  • I/O Interface IP Core

    IP Core

    I/O Interface IP Core

    Lattice Semiconductor’s IO Interface attribute acts as a memory interface to access valid addresses for GPO register writes and GPI register reads.
  • Mailbox IP Core

    IP Core

    Mailbox IP Core

    Lattice Semiconductor’s Mailbox IP functions as a memory interface, allowing access to valid addresses for GPO register writes and GPI register reads.
  • Internal Flash Controller IP Core

    IP Core

    Internal Flash Controller IP Core

    ​​The Lattice Internal Flash Controller for MachXO5-NX IP Core has a system bus interface to access the registers.​
    Internal Flash Controller IP Core
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