Lattice Propel Design Environment

Build FPGA-based Processor Systems in Minutes

Design Environment for Lattice FPGA-based Processor System Design - Lattice Propel is a complete set of graphical and command-line tools to create, analyze, compile, and debug both the hardware design of an FPGA-based processor system, and the software design for that processor system.

Lattice Propel Builder - An easy to use system IP integration environment, Propel Builder provides tools to integrate processors and peripheral IP. The graphical integration environment features an easy-to-use, drag and drop correct-by-construction methodology. All commands are Tcl scriptable.

Lattice Propel SDK - A seamless software development environment, Propel SDK is a software development kit (SDK) with an integrated industry standard IDE and toolchain. The SDK features SW/HW debugging capabilities along with software libraries and board support packages (BSP) for Propel Builder defined systems.

Features

  • Drag and drop IP instantiation
  • Correct by construction design methodology
  • High productivity HW/SW debugging
  • Software libraries and BSP support
  • Tcl scripting commands

Getting Started

  1. Download: Choose and download software from the Software Downloads & Documentation table below
  2. Install: Follow the installation guide, found in Software Downloads & Documentation section below.
  3. License: You will need a Lattice Propel license, Click the button below to request a license.

Jump to

Block Diagrams

Lattice Propel Design Environment

Lattice Propel Design Environment

Lattice Propel Builder Design Flow

Lattice Propel Design Flow

Lattice Propel Solutions

Lattice Sentry I2C Filter IP Core

IP Core

Lattice Sentry I2C Filter IP Core

SMBus relay with I2C filter and provides 4 interface to protect malicious traffic.
Lattice Sentry I2C Filter IP Core
Lattice Sentry PLD Interface IP Core

IP Core

Lattice Sentry PLD Interface IP Core

Lattice Semiconductor Customer Programmable Logic Devices (PLD)implements a bidirectional mailbox for sending and receiving messages.
Lattice Sentry PLD Interface IP Core
Lattice Sentry SMBus Mailbox IP Core

IP Core

Lattice Sentry SMBus Mailbox IP Core

SMBus, a two-wire interface that support fairness arbitration and compatible with AHB-Lite specification. Target devices are Mach-NX and MachXO3D.
Lattice Sentry SMBus Mailbox IP Core
PIC IP Core

IP Core

PIC IP Core

Lattice Semiconductor PIC soft IP with configurable 1~8 interrupt inputs and 32-bit AHB-L interface for Mach-NX FPGA
PIC IP Core
SFB Interface IP Core

IP Core

SFB Interface IP Core

SFB allow access to AHB-L CPLD block , management CPU recovery circuit and Flash sector for read/write.
SFB Interface IP Core

Award

Leadership in Engineering Achievement Program (LEAP) Awards 2020

Gold Medal- Software Category

Software Downloads & Documentation

Quick Reference
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
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ModelSim Lattice-Edition Usage Guidelines and Tips
FPGA-AN-02053 1.0 10/31/2022 PDF 1.9 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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ModelSim Lattice-Edition Usage Guidelines and Tips
FPGA-AN-02053 1.0 10/31/2022 PDF 1.9 MB
Lattice Propel 1.0 API Reference
FPGA-AN-02027 1.0 6/3/2020 PDF 914.5 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Lattice Propel 2022.1 Installation for Linux User Guide
FPGA-AN-02057 1.0 12/5/2022 PDF 761.2 KB
Lattice Propel 2022.1 Installation for Windows User Guide
FPGA-AN-02056 1.0 12/5/2022 PDF 1.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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RISC-V MC CPU IP - Lattice Propel Builder 2022.1
FPGA-IPUG-02210 1.0 12/5/2022 PDF 523.8 KB
RISC-V RX CPU IP - Lattice Propel Builder 2022.1
FPGA-IPUG-02211 1.0 12/5/2022 PDF 532.7 KB
RISC-V SM CPU IP - Lattice Propel Builder 2022.1
FPGA-IPUG-02212 1.0 12/5/2022 PDF 454.2 KB
DC-SCM LVDS Tunneling Protocol and Interface IP Core - User Guide
FPGA-IPUG-02200 1.3 12/26/2022 PDF 1.3 MB
AXI4 Interconnect Module - Lattice Propel Builder
FPGA-IPUG-02196 1.1 12/5/2022 PDF 1.3 MB
AXI4 to AHB-Lite Bridge Module - Lattice Propel Builder
FPGA-IPUG-02199 1.1 12/5/2022 PDF 805 KB
AXI4 to APB Bridge Module - Lattice Propel Builder
FPGA-IPUG-02198 1.1 12/5/2022 PDF 730.2 KB
Clock Reset Generator VIP - Lattice Propel Builder
FPGA-IPUG-02147 1.0 12/8/2020 PDF 1.1 MB
UART Model VIP - Lattice Propel Builder
FPGA-IPUG-02146 1.1 12/8/2020 PDF 1.1 MB
Timer/Counter IP Core – Lattice Propel Builder
FPGA-IPUG-02139 1.1 12/15/2021 PDF 453 KB
Lattice Propel 2022.1 SDK User Guide
FPGA-UG-02176 1.0 12/5/2022 PDF 2.8 MB
Lattice Propel 2022.1 Builder User Guide
FPGA-UG-02177 1.0 12/5/2022 PDF 5.2 MB
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Lattice Propel Product Brochure
IO272 2.0 9/29/2022 PDF 1.8 MB
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Lattice Propel 2022.1 Release Notes
FPGA-AN-02058 1.0 12/5/2022 PDF 726.6 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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A Step-By-Step Approach to Lattice Propel
FPGA-AN-02052 1.0 9/29/2022 ZIP 7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Lattice Propel Helps Designers Create Processor-Based Systems in Minutes
WP0029 1.0 2/23/2021 PDF 503.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Lattice Propel 2022.1 64-bit for Linux
2022.1 12/5/2022 ZIP 1.5 GB
Lattice Propel 2022.1 64-bit for Windows
2022.1 12/5/2022 ZIP 1.3 GB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

Licensing

Currently, Lattice Propel Design Environment only requires a Free License.

Notice: If you are upgrading to Propel 2022.1 or later and generated your free Propel license prior to December 2022, please generate a new license to enable proper usage of all tools included in Propel.

Device Support

Device Support by License
Product Subscription License Free License
Avant-E
Check Mark
CertusPro-NX
Check Mark
Certus-NX
Check Mark
CrossLink-NX
Check Mark
Mach-NX
Check Mark
MachXO5-NX
Check Mark
MachXO3D
Check Mark
MachXO3LF
Check Mark
MachXO3L
Check Mark
MachXO2
Check Mark
Operating System
Windows
Windows 10
Linux
RHEL 7.7
RHEL 8.4
Ubuntu 20.04 LTS
 
Request License

Propel Feature List

  • Propel Builder – Graphical driven IP integration and system building tool drag and drop instantiation and wizard guided configuration and parameterization.
  • Propel SDK – Software development kit with Industry-standard IDE and toolchain with integrated Gnu Debugging (GDB).
  • Templates for Hello World project
  • System-level functional verification environment for templates

Version History

Click here to see all Propel Version History.

Videos

Lattice Propel Thumbnail
Expand Video

Get Started Quickly with Lattice Propel

Lattice Propel is the Embedded Design Environment to implement RISC-V soft processor systems in Lattice FPGAs. This demonstration will guide you through building an embedded design, developing the software for the processor, implementation in the FPGA, and debugging the system all with in the Propel environment.
Propel Demo Thumbnail
Expand Video

Propel Simplifies Mach-NX Design

Use Lattice Propel software to add advanced security to a system control FPGA design quickly
Lattice Propel Training Series

Lattice Propel Design Environment Video Training Series

The Lattice Propel Design Environment Video Training Series is a multi-part video series covering every aspect of Propel development suite which includes Propel Builder and Propel SDK. It is well suited for both experienced and new users wanting to learn to develop SoC project using Propel and how to integrate the projects with Radiant and Diamond tools.