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  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
    RISC-V MC CPU IP Core
  • RISC-V RX CPU IP Core

    IP Core

    RISC-V RX CPU IP Core

    Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.
    RISC-V RX CPU IP Core
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • Lattice Sentry Demo Board for Mach-NX

    Board

    Lattice Sentry Demo Board for Mach-NX

    A complete platform to help you develop and test a NIST 800-193-compliant PFR solution. Includes numerous features to enable debug, interface and expansion
    Lattice Sentry Demo Board for Mach-NX
  • Lattice Sentry Demo Board for MachXO3D

    Board

    Lattice Sentry Demo Board for MachXO3D

    A complete platform to help you develop and test a NIST 800-193-compliant PFR solution. Includes numerous features to enable debug, interface and expansion
    Lattice Sentry Demo Board for MachXO3D
  • eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)

    IP Core

    eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)

    This IP core solution uses the CL-NX FPGA’s built-in transceiver for USB 3.1 and ULPI PHY for USB 2.0. It supports SuperSpeed, High Speed and Full Speed modes.
    eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)
  • RISC-V Single Core Linux (SCL) Processor

    IP Core

    RISC-V Single Core Linux (SCL) Processor

    RISC-V Single Core Linux processor includes everything required for running Linux on Lattice FPGAs and supports the RV32IMAC and RV32GC architecture.
    RISC-V Single Core Linux (SCL) Processor
  • USB 2.0 Device Controller IP Core (USB20SF)

    IP Core

    USB 2.0 Device Controller IP Core (USB20SF)

    USB20SF IP core provides FIFO interface for Data Endpoints while AHB Lite interface for Control Endpoint. This IP core supports High Speed and Full Speed modes
    USB 2.0 Device Controller IP Core (USB20SF)
  • KONDOR AX Development Board

    Board

    KONDOR AX Development Board

    ECP5 board for system design of HetNet, Industrial IoT, Cameras and Display applications
    KONDOR AX Development Board
  • ​​tinyCLUNX33 System on Module​

    Board

    ​​tinyCLUNX33 System on Module​

    ​​1x1" production ready, tightly integrated System on Module using Lattice CrossLinkU-NX (LIFCL-33U) to significantly reduce customers Time to Market.​
    ​​tinyCLUNX33 System on Module​
  • Pico-Ice

    Board

    Pico-Ice

    The Pico-Ice is a small, low-cost board with the Raspberry Pi Pico processor (RP2040) and a Lattice Semiconductor iCE40UP5K FPGA.​
    Pico-Ice
  • UPduino v3.1

    Board

    UPduino v3.1

    The UPDuino v3.1 is a small low-cost board featuring the Lattice iCE40 UltraPlus (ICE40UP5K) and an on-board FPGA programmer, flash, and LED with all FPGA pins.
    UPduino v3.1
  • LatticeMico32 Open, Free 32-Bit Soft Processor

    IP Core

    LatticeMico32 Open, Free 32-Bit Soft Processor

    A 32-bit Harvard, RISC architecture soft microprocessor, available for free with an open IP core license. Many compatible modules and IP are available.
    LatticeMico32 Open, Free 32-Bit Soft Processor
  • Long Range (LoRa) Wireless

    Reference Design

    Long Range (LoRa) Wireless

    Implement a LoRa compliant device using a tiny iCE40 UltraPlus FPGA, for low-power, low-footprint wireless communication over miles
    Long Range (LoRa) Wireless
  • OrangeCrab

    Board

    OrangeCrab

    This tiny ECP5 board follows the slim feather board specification. Includes DDR3 memory and compatible with open source toolchains. Great for RISC-V development.
    OrangeCrab
  • PQSubSys IP Core

    IP Core

    PQSubSys IP Core

    SCA-Secured Post-Quantum Cryptography Subsystem for lattice based NIST algorithms (Kyber, Dilithium, SHA3, SHAKE, all levels).
    PQSubSys IP Core
  • MachXO2 I2C Embedded Programming Access Firmware

    Reference Design

    MachXO2 I2C Embedded Programming Access Firmware

    Provides C code for interfacing to MachXO2 from a microcontroller, and RTL for implementing I2C between an external master and the MachXO2
    MachXO2 I2C Embedded Programming Access Firmware
  • Lattice Mico8 Open, Free Soft Microcontroller

    IP Core

    Lattice Mico8 Open, Free Soft Microcontroller

    8-bit microcontroller primarilyi targeted to the MachXO2 and MachXO3 families, but portable to other FPGAs. Full 18-bit wide instruction set and 32 registers
    Lattice Mico8 Open, Free Soft Microcontroller
  • LatticeMico8 to WISHBONE Interface Adapter

    Reference Design

    LatticeMico8 to WISHBONE Interface Adapter

    Provides logic to adapt the Lattice Mico8 (LM8) external I/O to a WISHBONE master interface
    LatticeMico8 to WISHBONE Interface Adapter
  • SPI GPIO Expander

    Reference Design

    SPI GPIO Expander

    Expand microprocessor general purpose I/O ports with a Serial Peripheral Interface (SPI)
    SPI GPIO Expander
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