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  • DC-SCM LVDS Tunneling Protocol and Interface IP Core

    IP Core

    DC-SCM LVDS Tunneling Protocol and Interface IP Core

    LTPI IP Core is an Open Computer Project Data Center – Secure Control Module Standards compatible solution which is introduced in the DC-SCM 2.0 Specification.
    MachXO3, MachXO3D 
    CRC, LVDS, LTPI, AMBA, APB, Lattice Diamond, Lattice Radiant 
    DC-SCM LVDS Tunneling Protocol and Interface IP Core
  • LVDS Tunneling Protocol and Interface Reference Design

    Reference Design

    LVDS Tunneling Protocol and Interface Reference Design

    The DC-SCM 2.0 LTPI Reference Design provides multiple solution compliant with DC-SCM 2.0 with a standardized DC-SCI and aggregating multiple data channels.
    MachXO3, MachXO3D 
    CRC, LVDS, I2C, GPIO, UART, LTPI, AMBA, APB, Lattice Diamond, Lattice Propel 
    LVDS Tunneling Protocol and Interface Reference Design
  • I2C to APB Bridge Reference Design

    Reference Design

    I2C to APB Bridge Reference Design

    With support APB read / write capability, the I2C to APB Bridge Reference Design converts external I2C Master into APB Master transaction.
    MachXO2, MachXO3, MachXO3D 
    I2C, APB, AMBA, AHB 
    I2C to APB Bridge Reference Design
  • Generic Soft SPI Master Controller Reference Design

    Reference Design

    Generic Soft SPI Master Controller Reference Design

    Provides an interface between a generic processor with parallel bus interface and external SPI devices.
    MachXO2, MachXO3, LatticeECP3, ECP5 / ECP5-5G, CrossLink, CrossLink-NX, iCE40 UltraPlus 
    SPI, Wishbone, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets 
    Generic Soft SPI Master Controller Reference Design
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    The RISC-V SM CPU IP processes data and instructions while considering the external interrupts. The CPU core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    Certus-NX, CrossLink-NX, MachXO3D, MachXO3, MachXO2, Avant-E 
    AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive 
    RISC-V SM CPU IP Core
  • Soft I2C Bus Master

    Reference Design

    Soft I2C Bus Master

    Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families
    CrossLink, CrossLink-NX, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 UltraPlus, LatticeECP3, MachXO2, MachXO3, Mach-NX 
    5G, Computing, IoT, TOR Switch, Bus Controllers, I2C 
    Soft I2C Bus Master
  • Soft I2C Master and Slave – Simple Write and Read

    Demo

    Soft I2C Master and Slave – Simple Write and Read

    Demonstrates the operation of an I2C Master and Slave doing simple write and read of data.
    iCE40 UltraPlus, MachXO3 
    Computing, IoT, TOR Switch, Bus Controllers, I2C 
    Soft I2C Master and Slave – Simple Write and Read
  • Soft I2C Slave Peripheral

    Reference Design

    Soft I2C Slave Peripheral

    Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families
    CrossLink, CrossLink-NX, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 UltraPlus, LatticeECP3, MachXO2, MachXO3 
    5G, Computing, IoT, TOR Switch, Bus Controllers, I2C 
    Soft I2C Slave Peripheral
  • Generic Soft SPI Master Controller Demonstration

    Demo

    Generic Soft SPI Master Controller Demonstration

    This demo implements the Generic Soft SPI Master Controller Reference Design by performing simple transactions to the external SPI Flash device found in the MachXO3-9400 Development Board
    MachXO2, MachXO3, LatticeECP3, ECP5 / ECP5-5G, CrossLink, CrossLink-NX, iCE40 UltraPlus 
    SPI, Wishbone, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets 
    Generic Soft SPI Master Controller Demonstration
  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    MachXO, LatticeXP2, ispMACH 4000ZE, MachXO2, LatticeECP3, Platform Manager, ECP5 / ECP5-5G, MachXO3 
    Bus Controllers, I2C, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, 5G 
    I2C Bus Master
  • I2C Master - WISHBONE Compatible

    Reference Design

    I2C Master - WISHBONE Compatible

    Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus
    MachXO, MachXO2, LatticeXP2, LatticeECP3, ECP5 / ECP5-5G, MachXO3 
    I2C, Wishbone, Bus Controllers, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, 5G 
    I2C Master - WISHBONE Compatible
  • I3C-S-MIPI-I3C-Basic-Slave-Controller

    IP Core

    I3C-S-MIPI-I3C-Basic-Slave-Controller

    Highly featured, SDR-Capable and HDR-Tolerant Slave controller. Supports hot-join, in-band interrupts, & dynamic addressing. Works to any Lattice FPGA device.
    MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 
    I3C, MIPI 
    I3C-S-MIPI-I3C-Basic-Slave-Controller
  • JPEG-DX-F - Ultra-Fast Baseline and Extended JPEG Decoder

    IP Core

    JPEG-DX-F - Ultra-Fast Baseline and Extended JPEG Decoder

    Scalable, ultra-high throughput 8/12-bit JPEG decoder. Ideal for low-latency motion-Jpeg streaming. Full-HD or Ultra-HD capable depending on the device.
    MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 
    Data Compression, JPEG, JPEG CODEC 
    JPEG-DX-F - Ultra-Fast Baseline and Extended JPEG Decoder
  • JPEG-DX-S - Baseline and Extended JPEG Decoder

    IP Core

    JPEG-DX-S - Baseline and Extended JPEG Decoder

    Compact, 8bit and 12bit per color, JPEG decoder. Ideal for low-latency motion-Jpeg streaming.
    MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 
    Data Compression, JPEG, JPEG CODEC 
    JPEG-DX-S - Baseline and Extended JPEG Decoder
  • JPEG-EX-F - Ultra-Fast Baseline and Extended JPEG Encoder

    IP Core

    JPEG-EX-F - Ultra-Fast Baseline and Extended JPEG Encoder

    Scalable, ultra-high throughput 8/12-bit encoder. Highly configurable with advanced bit-rate control. Ideal for low-latency motion-Jpeg streaming.
    MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 
    Data Compression, JPEG, JPEG CODEC 
    JPEG-EX-F - Ultra-Fast Baseline and Extended JPEG Encoder
  • JPEG-EX-S - Baseline and Extended JPEG Encoder

    IP Core

    JPEG-EX-S - Baseline and Extended JPEG Encoder

    Compact, 8bit and 12bit per color, JPEG encoder. Highly configurable with advanced bit-rate control features. Ideal for low-latency motion-Jpeg streaming.
    MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 
    Data Compression, JPEG, JPEG CODEC 
    JPEG-EX-S - Baseline and Extended JPEG Encoder
  • SPMI-CTRL - MIPI SPMI Master or Slave Controller

    IP Core

    SPMI-CTRL - MIPI SPMI Master or Slave Controller

    Highly featured, easy-to-use master or slave controller supporting the latest version of the MIPI-SPMI specification. Portable to any Lattice FPGA device
    MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 
    Power Management Bus, Power Management, MIPI, SPMI 
    SPMI-CTRL - MIPI SPMI Master or Slave Controller
  • TSN-EP – TSN Ethernet Endpoint Controller

    IP Core

    TSN-EP – TSN Ethernet Endpoint Controller

    Highly flexible core supports timing synchronization (IEEE 802.1AS), traffic shaping (IEEE 802.1Qav, Qbv) and frame-preemption (IEEE 802.1Qbu, & 802.3br).
    MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 
    IEEE1588, Ethernet, IEEE 802.3, Automotive, Functional Safety, TSN 
    TSN-EP – TSN Ethernet Endpoint Controller
  • UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack

    IP Core

    UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack

    Standalone, processor-less operation with up to 32 Rx and 32 Tx channels. Supports DHCP, IGMP, ICMP, ARP with cache, Jumbo and super Jumbo IPv4 frames.
    MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 
    Ethernet, IEEE 802.3, JPEG, Video Tx/Rx 
    UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack
  • MachXO3-9400 Development Board

    Board

    MachXO3-9400 Development Board

    General purpose evaluation and development for MachXO3, supporting hardware management demos with Lattice ASC plus Raspberry Pi and Arduino board connectors
    MachXO3, Platform Manager 2 & L-ASC10 
    Arduino, Breakout, Mixed-Signal, Raspberry Pi, Versa Connector, TOR Switch 
    MachXO3-9400 Development Board
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