Lattice Solutions

Everything you need to quickly and easily complete your design

Share This Result >

Narrow Your Results



Solution Type



Device Support

























Tags























































































Providers





Clear All
  • Power Sequencing with Fault Logging Demo

    Demo

    Power Sequencing with Fault Logging Demo

    Uses L-ASC10 to monitor, sequence four separate Power Planes from a central control point. Logs faults with timestamps. Expandable.
    Power Sequencing with Fault Logging Demo
  • ​​eSPI Target IP Core​

    IP Core

    ​​eSPI Target IP Core​

    ​​Lattice eSPI Target IP Core is compliant with the Intel eSPI specifications & has its own virtual wire channel in the user interface.​
    ​​eSPI Target IP Core​
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
    RISC-V MC CPU IP Core
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • Lattice Sentry 4.0 SCM and HPM CPLD Reference Design

    Reference Design

    Lattice Sentry 4.0 SCM and HPM CPLD Reference Design

    ​​This is a CPLD design template for the Secure Control Module (SCM) and Host Platform Module (HPM) for the Sentry 4.0 Server solution platform.​
    Lattice Sentry 4.0 SCM and HPM CPLD Reference Design
  • MPESTI Initiator Reference Design

    Reference Design

    MPESTI Initiator Reference Design

    MPESTI Initiator Reference Design provides the solution template which is compliant with the MPESTI Base Specification.
    MPESTI Initiator Reference Design
  • APB to AHB-Lite Bridge Reference Design

    Reference Design

    APB to AHB-Lite Bridge Reference Design

    The APB to AHB-Lite Bridge Reference Design provides an interface between the low power APB and the high-speed AHB-Lite.
    APB to AHB-Lite Bridge Reference Design
  • DC-SCM LVDS Tunneling Protocol and Interface IP Core

    IP Core

    DC-SCM LVDS Tunneling Protocol and Interface IP Core

    LTPI IP Core is an Open Computer Project Data Center – Secure Control Module Standards compatible solution which is introduced in the DC-SCM 2.0 Specification.
    DC-SCM LVDS Tunneling Protocol and Interface IP Core
  • LVDS Tunneling Protocol and Interface Reference Design

    Reference Design

    LVDS Tunneling Protocol and Interface Reference Design

    The DC-SCM 2.0 LTPI Reference Design provides multiple solution compliant with DC-SCM 2.0 with a standardized DC-SCI and aggregating multiple data channels.
    LVDS Tunneling Protocol and Interface Reference Design
  • SSPI Embedded Programming using RPi Reference Design

    Reference Design

    SSPI Embedded Programming using RPi Reference Design

    SSPI Embedded Programming reference design provides several benefits, such as low power consumption and reasonable CPU, GPU, and memory performance.
    SSPI Embedded Programming using RPi Reference Design
  • I2C to APB Bridge Reference Design

    Reference Design

    I2C to APB Bridge Reference Design

    With support APB read / write capability, the I2C to APB Bridge Reference Design converts external I2C Master into APB Master transaction.
    I2C to APB Bridge Reference Design
  • SPI Sub IP Core

    IP Core

    SPI Sub IP Core

    The SPI Sub IP Core is a versatile, efficient solution for SPI communication between an FPGA and a microcontroller, SoC, or another FPGA.
    AXI, SPI 
    SPI Sub IP Core
  • Soft I2C Bus Master

    Reference Design

    Soft I2C Bus Master

    Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families
    Soft I2C Bus Master
  • Soft I2C Master and Slave – Simple Write and Read

    Demo

    Soft I2C Master and Slave – Simple Write and Read

    Demonstrates the operation of an I2C Master and Slave doing simple write and read of data.
    Soft I2C Master and Slave – Simple Write and Read
  • Soft I2C Slave Peripheral

    Reference Design

    Soft I2C Slave Peripheral

    Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families
    Soft I2C Slave Peripheral
  • System Memory Module IP Core

    IP Core

    System Memory Module IP Core

    Propel IP Module: Configures Embedded Block RAMs or Distributed Memory interfaces and connects to the AHB-Lite bus.
    System Memory Module IP Core
  • UART IP Core

    IP Core

    UART IP Core

    Propel IP Module: Similar to NS16450 UART for serial communication supporting RS-232.
    UART IP Core
  • Generic Soft SPI Master Controller Demonstration

    Demo

    Generic Soft SPI Master Controller Demonstration

    This demo implements the Generic Soft SPI Master Controller Reference Design by performing simple transactions to the external SPI Flash device found in the MachXO3-9400 Development Board
    Generic Soft SPI Master Controller Demonstration
  • Page 1 of 3
    First Previous
    1 2 3
    Next Last