​​M-PESTI Initiator IP Core​

​​Early Peripheral Presence Detection and Attribute Collection Before System Boot up​

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The Modular Peripheral Sideband Tunneling Interface (M-PESTI) IP core provides early peripheral presence detection and attribute collection before system boot up. This IP core supports bidirectional communication with initiator command and target response structure.

Resource Utilization details are available in the IP Core User Guide.

Features

  • Communicates via half-duplex bidirectional UART protocol at 250k baud rate, 8-bit data, 1-bit odd parity, 1 start bit and 1 stop bit M-PESTI port.
  • Supports Static Discovery payload with CRC-8 payload checksum.
  • Supports one initiator to many targets system.
  • Supports configurable number of M-PESTI devices up to 64 targets.
  • Supports autonomous Static Discovery Payload request command to all Targets on round robin manner during Discovery phase.

Block Diagram

​M-PESTI Initiator IP Core Block DiagramExpand Image

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
MachXO5-NX MPESTI-I-XO5-UT MPESTI-I-XO5-US

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the M-PESTI Initiator IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
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M-PESTI Initiator IP User Guide
FPGA-IPUG-02258 1.1 12/20/2024 PDF 1.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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M-PESTI Initiator IP Release Notes
FPGA-RN-02005 1.1 12/20/2024 PDF 190.9 KB

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