Holoscan Sensor Bridge on NVIDIA Jetson Thor™: Multi-Sensor Connectivity for Physical AI
This demo showcases the Holoscan Sensor Bridge (HSB) on NVIDIA Jetson Thor, enabling low-latency, multi-sensor connectivity for Physical AI applications. The demonstration highlights how the HSB efficiently connects multiple high-bandwidth sensor data streams to an edge AI computing platform with minimal overhead, helping ensure that real-time perception, sensor fusion, and AI-driven decision-making remain synchronized. By delivering high-speed, reliable sensor connectivity, the solution supports the demanding performance requirements of next-generation robotics, autonomous systems, and intelligent edge applications.
Date: October 21, 2026 (English) Watch Now
Lattice Certus™-N2 Video Bridging: MIPI CSI-2 Camera to 10GbE Streaming over AVTP
This Certus-N2 demonstration showcases real-time video capture from a MIPI CSI-2 camera, with video data converted into AVTP payloads and transmitted over a 10G Ethernet link. The received Ethernet stream is processed on the Avant Versa platform for video processing and displayed via HDMI output.
Date: October 21, 2026 (English) Watch Now
12G-SDI Video Passthrough on Lattice Avant™-X 70 for Professional Video and Broadcast
This demo showcases 12G-SDI video passthrough on the Lattice Avant-X 70 FPGA for professional video and broadcast applications. The solution demonstrates reliable 12G-SDI video transmission, delivering the bandwidth and performance required for high-resolution video workflows. Designed to meet customer requirements for 12G-SDI connectivity, the demo highlights the capability of the Avant-X platform to support next-generation broadcast and professional AV systems.
Date: October 21, 2026 (English) Watch Now
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USB 3.2 Gen2 10 Gbps UVC Reference Design on Lattice CertusPro™-NX
This demo showcases a fully integrated SuperSpeed USB Type-C controller operating at 5 Gbps and 10 Gbps, implemented entirely within the FPGA without requiring an external USB 3.0 PHY or controller chip. The demonstration features a composite USB Video Class (UVC) implementation using an on-FPGA test pattern generator and includes a CSI-2 camera interface provisioned for future live-sensor integration. The solution highlights the flexibility, integration, and performance advantages of implementing high-speed USB connectivity directly within the FPGA.
Date: October 21, 2026 (English) Watch Now
Lattice Mach™-N2 DQ CNSA 2.0 Support: Post-Quantum Cryptography with ML-DSA and AES-256
This demo showcases the Lattice Mach-N2 Post-Quantum Cryptography (PQC) solution implemented on a Lattice Mach-N2 RoT Series FPGA. The demonstration highlights quantum-resistant security using ML-DSA (FIPS 204) for key generation, digital signing, and signature verification to authenticate messages, and ML-KEM (FIPS 203) for secure key establishment to protect the device root of trust against future quantum-based attacks. For data confidentiality, the design also incorporates AES-256 encryption and decryption. Together, these engines implement the CNSA 2.0-approved quantum-resistant algorithm suite, delivering crypto-agile, post-quantum-ready security in a compact, low power FPGA platform.
Date: October 21, 2026 (English) Watch Now
Lattice Mach™-N2 as a Network Interface Card: PCIe Gen4 x4 to Gigabit Ethernet Bridge
This demo showcases the Lattice Mach-N2™ FPGA functioning as a Network Interface Card (NIC), bridging data transfer between a PCIe Gen4 x4 interface and a Triple-Speed Ethernet (TSE) MAC RGMII interface. The demonstration highlights high-speed data movement, efficient protocol bridging, and the flexibility of Mach-N2 devices for networking and connectivity applications.
Date: October 21, 2026 (English) Watch Now
Lattice PCIe GDMA: Compact, Low-Latency General Purpose DMA IP for Lattice Nexus™ and Lattice Avant™ FPGAs
This demo showcases the Lattice GDMA Core, a soft IP core for PCIe subsystems designed for general-purpose PCIe DMA applications. Learn how GDMA delivers high-throughput, low-latency data transfers, making it well suited for demanding applications such as industrial control. The demo also highlights GDMA's rich feature set, XDMA compatibility, and industry-leading small footprint, enabling efficient and high-performance PCIe data movement.
Date: October 21, 2026 (English) Watch Now
Panoramic HUD 3-in-1 Solution: Icon Display with Functional Safety, Image Warping, and Local Dimming
This solution is specially developed for PHUD and WHUD, supporting icon overlay, detection and replacement, geometric distortion correction, and local dimming.
Date: October 21, 2026 (English) Watch Now
Camera Monitor System (CMS): Low-Latency FPGA Video Pipeline on Lattice CertusPro™-NX
Lattice's in-house ISP replaces mirror-based Camera Monitor Systems with a low-latency, low power FPGA video pipeline for automotive and industrial applications.
Date: October 21, 2026 (English) Watch Now
DC-MHS Host Processor Module with Lattice FPGA for Plug-and-Play Interoperability Using LTPI and M-PESTI
This demonstration shows a Lattice FPGA on a Data Center Modular Hardware System (DC-MHS) Host Processor Module (HPM), using the LVDS Tunneling Protocol and Interface (LTPI) and M-PESTI. It illustrates how standardized, modular interfaces enable plug-and-play interoperability across server building blocks.
Date: October 21, 2026 (English) Watch Now
OBMF-ICP Deployment on a 33U System for Rack-Level Management
This demonstration shows an OBMF-ICP deployment on a 33U system. It illustrates how the solution is implemented and managed at rack level in a data center environment.
Date: October 21, 2026 (English) Watch Now
ASPEED AST1840 with Lattice FPGA Evaluation Kit for Platform Management
This demonstration presents the ASPEED 1840 evaluation kit with a Lattice FPGA. The board enables secure server management and control. Its key features include an integrated Caliptra 2.1 Root of Trust, an Arm Cortex-M4 processor running at 400 MHz, and a 25k-LUT FPGA with 196 flexible I/Os.
Date: October 21, 2026 (English) Watch Now
Lattice Security Solutions Portfolio including Lattice Mach™-N2, Lattice Sentry™ 5, Lattice Security Retrofit, and Nuvoton OpenTitan
This presentation provides an overview of the Lattice security portfolio for data center platforms, including Lattice Mach-N2, Lattice Sentry 5, the Security Retrofit approach, and the Lattice and Nuvoton OpenTitan solution. It shows how each option helps customers add Root of Trust capabilities to new and existing designs.
Date: October 21, 2026 (English) Watch Now
USB I/O Aggregation with Lattice FPGAs for Consolidating Multiple USB Connections
This demonstration shows how a Lattice FPGA aggregates multiple USB I/O connections into a consolidated interface. It highlights the benefits of programmable logic for flexible I/O expansion and simplified system design.
Date: October 21, 2026 (English) Watch Now
CNSA 2.0 Post-Quantum Cryptography on Lattice Mach™-N2D: ML-DSA, ML-KEM, and AES-GCM
This demonstration shows a Lattice Mach-N2D device implementing post-quantum cryptography (PQC) aligned with the Commercial National Security Algorithm Suite 2.0 (CNSA 2.0). It illustrates how a Root of Trust can support quantum-resistant algorithms including ML-DSA digital signature, ML-KEM shared secret establishment, and AES-GCM for data encryption.
Date: October 21, 2026 (English) Watch Now
Lattice ORAN™ 5G Small Cell Open RAN Reference Demo
This demonstration presents a 5G small cell based on Open RAN (ORAN) principles, using Lattice programmable solutions. It shows how a flexible, low power FPGA platform can address the interface and processing needs of open, interoperable radio access network equipment.
Date: October 21, 2026 (English) Watch Now
Delta Networking Tomahawk 6 Switch with Lattice FPGAs for Programmable Platform Control
This demonstration shows how Lattice FPGAs support a Delta Networking switch built around Tomahawk 6. It highlights the role of low power programmable logic in system control, management, and I/O functions for high-bandwidth networking platforms.
Date: October 21, 2026 (English) Watch Now
Verified Quantum Entropy for Hardware Security with the Quside Entropy Module and a Lattice Root of Trust
This demonstration presents a verified quantum entropy source from Quside integrated with a Lattice RoT. It shows how high-quality, verifiable randomness can strengthen key generation and other cryptographic operations in data center hardware.
Date: October 21, 2026 (English) Watch Now
Post-Quantum Secure Server Platform with Lattice Sentry™ 5.0 on Lattice MachXO5T™-NX 55TDQ
This demonstration showcases a Lattice Sentry™ 5.0 solution that provides post-quantum cryptography (PQC) protection for platform firmware using the Lattice MachXO5T-NX 55TDQ device. It demonstrates how a Root of Trust (RoT) authenticates and safeguards firmware in data center platforms, helping protect against emerging quantum-era security threats.
Date: October 21, 2026 (English) Watch Now
Lattice Semiconductor: The Low Power Programmable and Platform Firmware Leader
For over 40 years, Lattice has led FPGA innovation as the #1 supplier of small FPGAs worldwide. Our compact, power-efficient solutions are trusted by tens of thousands of customers across the compute, communications, industrial, and embedded markets to build a secure, intelligent, and connected world.
Date: September 17, 2026 (English) Watch Now
Introducing Lattice Prompt
Lattice Prompt™ is an AI design assistant built for FPGA engineers. Describe your design intent in natural language, and it interfaces directly with Lattice Radiant® for compilation, simulation, and validation. Running as an open Model Context Protocol (MCP) server, it works with any capable IDE and all major large language models, so you keep full control of your toolchain. Every response is optimized for Lattice devices, grounded in authoritative Lattice documentation and real design expertise, with flows running through Radiant locally or over the network.
Date: September 16, 2026 (English) Watch Now
What’s New in Propel 2026.1
Discover what’s new in Lattice Propel 2026.1, featuring enhancements that improve user experience and streamline intuitive design creation. Watch now to see how the latest updates help you build FPGA-based embedded systems faster and focus on innovation.
Date: June 26, 2026 (English) Watch Now
What’s New in Radiant 2026.1
Lattice Radiant 2026.1 is purpose-built to help designers maximize productivity for small and mid-range FPGA designs. This release turbocharges development speed and drives unparalleled usability.
Date: June 26, 2026 (English) Watch Now
FPGA‑accelerated 3D Sensing for Humanoid Robot Manipulation
This demo showcases a miniaturized 3D sensor module built on AIRY3D’s patented TDM technology, mounted on a humanoid robotic arm and interfaced with the Lattice CrossLink™-NX 40 FPGA. The FPGA offloads the majority of depth computation, reducing system load and enabling efficient operation alongside an application processor such as the NVIDIA Jetson Orin™ Nano. With a wide field of view and no occlusion, the sensor delivers accurate near‑field depth awareness. This capability opens new opportunities for robotic grasping, in‑hand manipulation, and end‑effector‑mounted perception, supporting more responsive and intelligent humanoid robotics systems.
Multi‑sensor 10GbE Aggregation for NVIDIA Holoscan Using Lattice FPGAs
This demo highlights the DA322 Holoscan Adapter from Tauro Technologies, a compact multi‑sensor aggregation platform built on a low power Lattice CertusPro™‑NX FPGA. The solution supports four MIPI CSI‑2 camera inputs and aggregates HDMI, MIPI, or GMSL data into a single 10 GbE stream for efficient sensor ingest. Using RDMA, the platform feeds synchronized, high‑bandwidth data directly into NVIDIA Orin™ or Thor™ systems for real‑time visualization. With Precision Time Protocol (IEEE 1588‑2019), flexible multi‑function I/O, and an SFP+ 10 Gbps interface, the design enables scalable, space‑efficient sensor integration for advanced edge AI and visualization applications.
Real‑time 4K30 Embedded Vision Pipeline on Lattice Avant™ FPGAs
This demo showcases a real‑time 4K30 imaging pipeline implemented on the Lattice Avant FPGA platform, highlighting a complete embedded vision workflow from sensor input through FPGA‑based ISP processing to low‑latency HDMI output. The design demonstrates how Lattice Avant enables high‑performance, modular image signal processing that can be adapted to application‑specific requirements while maintaining real‑time operation. Designed for evaluation, rapid prototyping, and scalable camera development, the solution illustrates the flexibility and performance of Lattice Avant for next‑generation embedded vision systems.
Multi‑camera Aggregation for Real‑time Edge AI on Lattice Avant™ FPGAs
This demo showcases a scalable multi‑camera aggregation architecture using a Lattice Avant‑X FPGA and NVIDIA Hololink™ technology to enable ultra‑low‑latency sensor ingest for edge AI systems. Multiple camera streams are synchronized, aggregated, and preprocessed on the FPGA before being transmitted over standard 10 G or 25 G Ethernet to NVIDIA Thor™ for real‑time AI processing. By offloading camera handling, timestamping, and data conditioning from the host, the design reduces system overhead while delivering high‑bandwidth, deterministic performance. The demo highlights an AI‑ready pipeline optimized for demanding applications such as ADAS, robotics, aerospace, defense, and industrial vision.
SLVS‑EC 3.1 Image Sensor Interface on Lattice Avant™ FPGAs
This demo showcases an SLVS‑EC 3.1 image sensor interface implemented using Macnica’s SLVS‑EC IP on Lattice Avant-G and Avant-X FPGAs. Designed to support the latest Sony SLVS‑EC image sensors, the solution enables high‑performance, low‑power image capture in a compact FPGA footprint. The design supports backward compatibility with earlier SLVS‑EC standards, flexible pixel widths, multiple lane configurations, and ECC for secure data transmission. With built‑in features such as de‑skew and byte‑to‑pixel conversion, the demo highlights how Lattice Avant FPGAs simplify system design and accelerate evaluation of next‑generation high‑resolution imaging applications.
Aurora to 10G Ethernet Protocol Conversion on Lattice Avant™ FPGAs
This demo showcases an FPGA‑based protocol conversion solution from Lattice partner A.L.S.E that bridges Aurora high‑speed serial links to standard 10G Ethernet. Targeting imaging and data acquisition systems where Aurora is commonly used for low‑latency, high‑bandwidth data transfer, the design demonstrates a scalable alternative to custom PCIe boards for PC connectivity. Using a Lattice Avant Versa kit with dual SFP+ interfaces, the solution converts Aurora traffic to 10G Ethernet, simplifying system integration while maintaining performance and flexibility across heterogeneous protocols.
Single‑Chip EtherCAT® Motor Control on Lattice FPGAs
This demo showcases an integrated EtherCAT motor control solution implemented on a single Lattice FPGA, designed for real‑time motion control nodes in industrial automation systems. The design combines cyclic EtherCAT process data exchange with a deterministic field‑oriented control (FOC) motor control subsystem, delivering high‑dynamic performance with minimal latency. An embedded RISC‑V processor manages configuration and application control, while single‑chip integration consolidates EtherCAT communication, the FOC control loop, and encoder interfaces to reduce BOM, save board space, and improve system determinism.
Low Power PQC‑enabled FPGA and TPM Platform for Secure Physical AI
This demo showcases a joint Lattice, SEALSQ, and Promwad reference board designed to accelerate development of secure physical AI and industrial control systems. The platform combines a low power Lattice FPGA acting as a Root of Trust with a SEALSQ post‑quantum cryptography (PQC)‑compliant TPM, enabling secure boot, device attestation, and ongoing cyber‑resilient monitoring. With support for TPM 2.0 PQC extensions, anti‑tamper protection, and real‑time deterministic control, the reference design provides a practical foundation for building future‑ready systems that require strong security, flexibility, and rapid prototyping.
10BASE‑T1S Network Interoperability Demo on Lattice CertusPro™‑NX
This demo presents a 10BASE‑T1S Ethernet network evaluation platform developed with Canova Tech, showcasing throughput and interoperability across a mixed‑topology network. The design integrates Canova Tech’s 10BASE‑T1S Digital Controller IP synthesized on a Lattice CertusPro‑NX FPGA, with logic boards implementing MAC functionality, data handling, and control logic. A microcontroller manages system initialization, configuration, and MAC‑PHY interaction through standard interfaces, including OPEN Alliance and Media Independent Interface (MII). Together, the solution demonstrates a practical approach for validating 10BASE‑T1S Ethernet in automotive and industrial networking environments.
Full‑Bridge PCIe® Demo with NXP Hosts and Lattice Certus™ FPGAs
This demo highlights Lattice’s full‑bridge PCIe IP implemented on a Lattice Certus FPGA and demonstrated with NXP host processors. The FPGA appears as a standard PCIe endpoint with memory‑mapped BAR space, while also acting as a bus master capable of initiating transactions back to the host. A configurable application layer and embedded RISC‑V processor showcase mailbox‑based command handling, register access, and host‑to‑flash programming and verification over PCIe. By eliminating the need for an external bridge device, the design demonstrates how a single PCIe link enables efficient, bidirectional communication and remote update capabilities in NXP‑based systems.
Dual HPM Single SCM LTPI Demo
This demo showcases a high-performance LTPI setup using a single System Control Module (SCM) connected to two Host Processor Modules (HPMs) via the Lattice MachXO3™ device. It demonstrates efficient aggregation of low-speed signals—GPIO, UART, and I2C—from the SCM to both HPMs, with real-time link status monitoring and environmental sensing. Each LTPI link operates independently, ensuring uninterrupted CPLD functionality even if one HPM disconnects.
Lattice PQC Solution for Lattice MachXO5™-NX 55TDQ and PFR Demo
This demo highlights Lattice Semiconductor’s industry-first PQC-ready secure control FPGA, the Lattice MachXO5-NX 55TDQ, showcasing a single-chip solution that integrates attestation verifier, Platform Firmware Resiliency (PFR), and LTPI capabilities. Built on the power-efficient Lattice Nexus™ platform, the demo demonstrates robust post-quantum cryptography (PQC) support compliant with CNSA 2.0 and NIST standards, including ML-KEM and ML-DSA algorithms. It emphasizes crypto-agility, secure boot, hardware root of trust, and hybrid security models—making it ideal for datacenter, industrial, and communications infrastructure applications.
MPESTI Interoperability with Nuvoton and Renesas Fanout Controller Demo
This demo showcases Lattice Semiconductor’s implementation of the Modular Peripheral Sideband Tunneling Interface (MPESTI), a single-wire communication protocol developed under the Open Compute Project (OCP). It highlights seamless interoperability between a MPESTI Initiator and multiple target devices from Nuvoton and Renesas, connected via a fanout controller on the Lattice iCE40 UltraPlus™ board. The setup supports up to 64 endpoints, enables hot-plug capability, and eliminates the need for external MUX or switches—offering a scalable, cost-efficient solution for modular data center environments.
Onboarding LTPI Demo
The Onboarding LTPI Demo showcases Lattice’s seamless Plug and Play setup for Host Processor Module (HPM) endpoints using JSON-based onboarding. It highlights how LTPI bridges hardware differences between HPM and DC-SCM modules by combining I2C, UART, and GPIO into a unified high-speed interface. The demo features dynamic metadata capture, pre-link endpoint detection via a RISC-V I2C controller, and sensor interaction through a Raspberry Pi acting as a BMC—demonstrating scalable, interoperable integration for modern data center ecosystems.
Quantum Secure Key Exchange Demo
This demo showcases the establishment of a quantum-resistant secure communication channel using post-quantum cryptography (PQC) on the Lattice MachXO5™-55TDQ FPGA. It features ML-KEM for key exchange and ML-DSA for digital signing, simulating secure boot, mutual authentication, and encrypted data exchange over I2C. The setup includes pre-provisioned public keys, protection against impersonation and replay attacks, and aligns with SPDM 1.4 standards. Designed for crypto agility, the demo highlights Lattice’s commitment to future-proof firmware security in datacenter, industrial, and communications applications.
SEC-TPM with Lattice MachXO5™-NX
The SEC-TPM Demo showcases a single-chip Root of Trust solution, integrating traditional TPM functionality with post-quantum cryptography (PQC) and Platform Firmware Resilience (PFR). Running on a RISC-V core, the demo highlights secure credential management anchored to hardware, leveraging Lattice’s RNG and crypto-agile architecture. It eliminates the need for external TPM chips, simplifying the supply chain and enabling secure remote updates—making it ideal for next-generation server security applications.
Single Chip Solution for Attestation Verifier, PFR, and LTPI Demo
This demo showcases Lattice’s unified security solution built on the Lattice MachXO5™-NX 55TDQ device, integrating attestation verifier, Platform Firmware Resilience (PFR), and LTPI capabilities into a single chip. Leveraging the Lattice Sentry™ 4.0 platform, it supports both traditional cryptography and post-quantum algorithms (ML-DSA, ML-KEM), enabling secure image authentication, key exchange, and encrypted communication. The solution is compliant with SPDM 1.2, NIST 800-193, and CNSA 2.0 standards, and offers robust connectivity via I2C, I3C, SMBus, and LTPI—delivering scalable, crypto-agile protection for modern server platforms.
SPDM 1.2 Demo
The SPDM 1.2 Demo showcases the Lattice Sentry™ 4.0 platform’s robust hardware and firmware security capabilities through cryptographic attestation. Running on the Lattice MachXO5™-NX 55TDQ device, the demo verifies device identity and firmware integrity using SPDM 1.2 commands over I2C and I3C interfaces, including LTPI channels. It highlights a modular framework designed for future security upgrades, including SPDM 1.4 and post-quantum cryptography (PQC) with ML-KEM and ML-DSA support—demonstrating Lattice’s commitment to evolving cybersecurity standards.
USB to I/O Conversion Demo
The USB to I/O Conversion Demo showcases Lattice’s high-speed USB 2.0 connectivity solution built on the Lattice CrossLinkU™-NX FPGA, enabling seamless bridging between modern computing platforms and essential peripherals like GPIO, UART, and I2C. Supporting both CDC and MCTP USB classes, the demo highlights a scalable multi-endpoint architecture that manages up to three USB devices, ensuring robust system management and protocol flexibility. Designed for multi-node environments, this modular solution empowers developers with crypto-agile control and future-ready integration across industrial, embedded, and server applications.
Industrial HMI Demo: Intelligent Operator Recognition and Control
Experience a cutting-edge industrial human-machine interface (HMI) that features advanced operator attention sensing and identification. This demo enables seamless interaction with machinery, delivering real-time insights and precise control for enhanced operational efficiency.
Securing the Future: Cybersecurity Compliance and Global Standards
Learn the fundamentals of cybersecurity standards and regulations in this informative video. We break down the scope, key requirements, and essential security principles that organizations must follow to stay compliant and secure with leading agencies such as NIST, CISA, NSA, ENISA, ETSI, and the European Commission. Whether you're new to cybersecurity or looking to stay updated on regulatory expectations, this video provides a concise overview to help you navigate the landscape with confidence.
Lattice Semiconductor: Advancing Low Power FPGA Leadership
As the low power programmable leader, Lattice is at the forefront of FPGA innovation. We're committed to delivering industry-leading low power, high-performance, small footprint solutions as a steadfast, trustworthy partner to our customers worldwide.
Lattice Nexus™ 2 FPGA Platform
What’s New in Lattice Radiant™ 2024.2
Lattice Nexus™ 2 FPGA Platform: Power and Performance Leadership Demonstration
Lattice Nexus™ 2 FPGA Platform: Boot Up Demonstration
Lattice Nexus™ 2 FPGA Platform: Edge Sensor Monitoring Demonstration
Lattice Avant™-X FPGA: SERDES Demo
Lattice Avant™-X FPGA: Power Efficiency Demo
Lattice Avant™-G FPGA: Boot Up Time Demo
Glance by Mirametrix® Demonstration: Enhancing Safety and Reducing Errors in Industrial Applications
2023 Lattice Developers Conference: Opening Keynotes
Innovative Mid-Range FPGAs: Lattice Avant™-G and Lattice Avant™-X
Lattice Drive™ Solution Stack - Accelerate Automotive Application Development
Lattice Radiant – FPGA Design Complete Tools Suite
Lattice Semiconductor: Expanding Our FPGA Leadership
Accton Technology: Power Efficient FPGA Solutions, Lattice Avant™ Launch Event
NI: Power Efficient FPGA Solutions, Lattice Avant™ Launch Event
Rockwell Automation: Power Efficient FPGA Solutions, Lattice Avant™
Lattice Ecosystem Partners Share Excitement on Lattice Avant™
Lattice Avant™ FPGA Platform: AI Processing Demo
Lattice Avant™ FPGA Platform: Performance Demo
Lattice Avant™ FPGA Platform: Power Efficiency Demo
Lattice Avant™: The Next Level of FPGA Innovation
Lattice Avant™ FPGA Platform: Taking Low Power to New Heights
Lattice Semiconductor: Keynote Address at Embedded World 2022
Interview with Lattice Semiconductor: How FPGAs Solve Today’s Technology Trend Challenges
Introducing the Lattice Nexus Platform
Introducing CrossLink-NX
CrossLink-NX: Power Efficiency Demo
CrossLink-NX: Instant On Demo
Lattice Semiconductor: the low power programmable leader
Lattice MachXO3D: accelerating development of secure systems
Lattice sensAI: accelerating low power AI at the edge
Using eARC to Easily Enable Theater Quality Surround Sound
This video introduces the benefits of HDMI 2.1’s eARC feature:
- Higher bandwidth – 37M of audio that supports all audio formats
- Full home theater experience with the simplicity of operating a TV set
- Future proof receivers against changes in video standards
Building a Seamless 360 Degree Surround View with ECP5
This demonstration takes the output from four fish-eye cameras and performs de-warping, white balance correction, and image stitching. The demonstration also enables the user to provides different views.
Face Tracking Using ECP5 and CNNs | Lattice sensAI
This demonstration identifies and tracks a human face. The inferencing is done using Convolutional Neural Networks implemented in the Embedded Vision Development Kit’s ECP5 FPGA. Power consumption is less than 1W.
Human Presence Detection Using ECP5 and CNNs | Lattice sensAI
This demonstration processes video images and identifies the presence of a human. The inferencing is done using Convolutional Neural Networks implemented in the Embedded Vision Development Kit’s ECP5 FPGA. Power consumption is less than 1W.
Object Counting Using ECP5 and CNNs | Lattice sensAI
This demonstration tallies apples and oranges to demonstrate object counting. The inferencing is done using eight Convolutional Neural Networks implemented in the Embedded Vision Development Kit’s ECP5 FPGA. Power consumption is less than 1W.
Speed Sign Detection Using ECP5 and CNNs | sensAI
This demonstration looks for speed limit signs and interprets what is on the sign. The inferencing is done using Convolutional Neural Networks implemented in the Embedded Vision Development Kit’s ECP5 FPGA. Power consumption is less than 1W.
Fast Prototyping for Embedded Vision Applications
Learn how easy it is mix and match multiple I/O types with the modular VIP platform.
- Input options: HDMI, DisplayPort, Dual Sensor
- Output options: HDMI, DisplayPort, USB3-GbE
Using CrossLink to implement a MIPI DSI to LVDS bridge
Always-on Computing Demos from Lattice Semiconductor
Using Lattice CrossLink FPGA for 360 Surround View Applications
Enable Predictable Design Convergence with Lattice Radiant Software
Lattice Autonomous Robot Demo
Simplify Audio Connectivity with HDMI 2.1 eARC
CrossLink IP Cores for Mobile Influenced Markets
Lattice Embedded Vision Development Kit
We have combined the bridging capability of our CrossLink FPGA, the low-power, small form factor ECP5 and the high-resolution benefits of our HDMI ASSP, onto this modular platform. Learn about the specs of this development kit and let us help you enable flexible connectivity and energy efficient image processing for robotics, drones, ADAS, smart surveillance and AR/VR systems.
LATTICE at Embedded World 2017
Lattice Semiconductor showcases product solutions for connectivity and processing at the edge.
CrossLink 4:1 CSI-2 Aggregator IP Demo from Lattice Semiconductor
Learn more about Lattice's CrossLink FPGA and its new 4:1 MIPI CSI-2 camera aggregator bridge, ideal for drones, AR/VR, 360 cameras, and other automotive and industrial solutions.
Embedded Vision Solutions using Lattice Semiconductor Products
Learn how Lattice products support edge computing applications (video processing acceleration), sensor bridging for machine vision, and stereo vision for robotics and drones.
FPGAs in Automotive
Learn how FPGAs can support the needs of modern Advanced Driver Assistance Systems (ADAS) .
Stereo Vision for Robotics using Lattice Semiconductor Products
Lattice CrossLink FPGA, ECP5 FPGA and HDMI ASSP come together to provide one clean and efficient solution for video processing and delivery.
Lattice Automotive Solutions for ADAS
Using Lattice’s ECP5 FPGA device, we are able to take the images of multiple automotive cameras, stitch them together, and apply many enhancing/correcting benefits to output one final, clean image for the driver.
Signal Aggregation Solutions with Lattice iCE40 FPGAs
The iCE40 UltraPlus is the world’s smallest FPGAs with enhanced memory & DSPs for reduced system cost, lower power consumption & faster time-to-market. Our sensor data fusion with embedded RISC-V and multi-sensor aggregation demos show why iCE40 UltraPlus is a must for your next consumer device.
Signal Aggregation using Lattice Solutions
We are demonstrating video and audio signal aggregation in products using Lattice iCE40 FPGAs.
