IoTs and Wearables

Low Power, Small Size FPGAs Enable High Performance Devices with Distributed Processing And Flexible I/O Support

With deployment of smarter Internet of Things (IoT) devices and wearables, the number of sensors used is exploding. Lattice is helping IoT designers capture data from multiple sensors, analyze and deliver a powerful user experience with low power distributed processing engines and flexible I/Os supporting a wide range of sensors.

Lattice’s optimized low power FPGAs provide:

  • Low power on-device AI for object detection, identification, counting and human-machine interfacing
  • Flexible and low latency sensor data aggregation, bridging, data buffering, and processing from a wide variety of sensors
  • Programmable I/O expansion and aggregation to solves form factors and architectures challenges

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Block Diagram

IoT and Wearables

Example Use Cases

Low Power AI Processing

  • Low Power on-device NN based processing
  • Reduced data traffic to the cloud, improving security and privacy and reducing bandwidth usage
  • Object detection, classification, counting and HMI including gestures and voice based commands

Display Bridging

  • Bridge between displays and processor when display interface is not supported native by the processor
  • Use the FPGA internal memory resources for compression and buffering
  • Expand the number of processor display interfaces

Audio Bridging

  • Connect up to 8 microphones to a processor
  • Audio data buffering to offload the processor
  • Support I2S, PDM microphone interfacing
  • Up to 1 Mb of on device RAM for buffering

Image Sensor Bridging

  • Connect a wide variety of image sensors to processors
  • MIPI PHYs supports up to 2.5 Gbps/lane, up to four lanes
  • Flexible host interfacing including CSI, SPI, PCIe
  • Flexible processing for video data muxing and stitching

Sensor Fusion and I/O Expansion

  • Interface to a wide variety of sensors to create rich user experience
  • Flexible preprocessing including arbitration, time stamping, and filtering
  • Create programmable sensor fusion algorithms

Low Latency Sensor Bridging

  • Take advantage of parallel FPGA architecture to simultaneously collect data from multiple sensors
  • Interface to a wide variety of sensors to create rich user experience
  • Flexible preprocessing including arbitration, time stamping, and filtering

Reference Designs

ā€‹ā€‹Avant MIPI-to-Parallel and Parallel-to-MIPI Bridges Reference Designā€‹

Reference Design

ā€‹ā€‹Avant MIPI-to-Parallel and Parallel-to-MIPI Bridges Reference Designā€‹

ā€‹ā€‹The design allows quick interface for a processor with a MIPI DSI with an RGB interface, or camera with MIPI CSI-2 to a processor with parallel interfaceā€‹
ā€‹ā€‹Avant MIPI-to-Parallel and Parallel-to-MIPI Bridges Reference Designā€‹
Key Phrase Detection

Reference Design

Key Phrase Detection

Continuous searches for a key phrase utterance via a digital MEMS microphone. Can be re-configured to work with any trained word or phrase.
Key Phrase Detection
Human Face Identification Reference Design

Reference Design

Human Face Identification Reference Design

Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.
Human Face Identification Reference Design
Human Presence Detection

Reference Design

Human Presence Detection

Uses Lattice sensAI IP to continuously search for the presence of a human and reports results. Can be adapted to detect any other object.
Human Presence Detection
Object Counting AI

Reference Design

Object Counting AI

An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
Object Counting AI

Demos

Key Phrase Detection

Demo

Key Phrase Detection

Uses artificial intelligence (AI) to detect a specific key-phrase using a tiny, low-power iCE40 UltraPlus FPGA
Key Phrase Detection
CSI-2 PCIe Bridge Demonstration

Demo

CSI-2 PCIe Bridge Demonstration

This design demonstrates the functionality of transferring MIPI CSI-2 camera video data to computer via PCIe with a Direct Memory Access (DMA) engine.
CSI-2 PCIe Bridge Demonstration
Human Counting AI Demo

Demo

Human Counting AI Demo

Human upper-body detection and counting demonstration utilizes Latticeā€™s ECP5 FPGA and a Convolutional Neural Network (CNN) acceleration engine
Human Counting AI Demo
Human Face Detection AI Demo

Demo

Human Face Detection AI Demo

Uses Lattice sensAI IP to detect human faces on a tiny, low-power iCE40 UltraPlus FPGA implementing AI at the edge. Adaptable to detect other objects.
Human Face Detection AI Demo

IP Cores

Advanced CNN Accelerator IP

IP Core

Advanced CNN Accelerator IP

Calculates full layers of Neural Network including convolution layer, pooling layer, batch normalization layer, and fully connected layer.
Advanced CNN Accelerator IP
CNN Plus Accelerator IP Core

IP Core

CNN Plus Accelerator IP Core

CNN Plus IP is a flexible accelerator IP that simplifies implementation of Ultra-Low power AI by leveraging capabilities of Lattice FPGAs.
CNN Plus Accelerator IP Core
Convolutional Neural Network (CNN) Accelerator IP

IP Core

Convolutional Neural Network (CNN) Accelerator IP

Implement AI solutions with CNNs from common or custom networks. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
Convolutional Neural Network (CNN) Accelerator IP
Convolutional Neural Network (CNN) Compact Accelerator

IP Core

Convolutional Neural Network (CNN) Compact Accelerator

Implement AI solutions with CNNs or BNNs that have power consumption in the mW range. Works with Lattice Neural Network Compiler software tool.
Convolutional Neural Network (CNN) Compact Accelerator

Development Kits & Boards

CertusPro-NX Versa Board

Board

CertusPro-NX Versa Board

CertusPro-NX Versa Board supports a wide range industry standards such as MIPI, SFP+, 10 GbE, LPDDR4 and PCIe (Gen3) for rapid prototyping and testing.
CertusPro-NX Versa Board
Embedded Vision Development Kit

Board

Embedded Vision Development Kit

Three-board Video Interface Platform (VIP) modular kit. Includes 2 MIPI/D-PHY camera input, FPGA processing, HDMI output. More Input/Output boards available.
Embedded Vision Development Kit
CrossLink-NX Evaluation Board

Board

CrossLink-NX Evaluation Board

For general evaluation and development with CrossLink-NX, includes many flexible interfaces such as FMC and PMOD with generous device IO access
CrossLink-NX Evaluation Board
HM01B0 UPduino Shield

Board

HM01B0 UPduino Shield

A complete development kit for implementing Artificial Intelligence (AI) using vision and sound as sensory inputs to a low-cost, low-power iCE40 UltraPlus FPGA.
HM01B0 UPduino Shield

Support

Technical Support

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