CNN Plus Accelerator IP

AI Acceleration Using Low Power FPGAs

Customized convolutional neural network (CNN) IP – CNN Plus IP is a flexible accelerator IP that simplifies implementation of Ultra-Low power AI by leveraging the parallel processing capabilities, distributed memory and DSP resources of Lattice FPGAs.

Configurable modes of use - Two implementations are available, compact or high performance. Compact mode is the low power processing mode taking advantage of the FPGA local memory. On the other hand, the high performance mode is optimized for use with larger network implementations.

Easy to implement – Models trained using common machine learning frameworks such as TensorFlow can be compiled using the Lattice Neural Network Complier Tool and implemented on HW using the CNN Plus Accelerator IP.

Features

  • Performs a series of calculations per command sequence generated by the Lattice NN Compiler tool
  • Configurable resource usage for tradeoff between power and performance
  • Support common network structures such as VGG, Mobilenet, Resent and SDD
  • Takes advantage of internal and external memory resource and manages access to optimize performance
  • Configurable bit width of neural network weights (16 bit, 8 bit, 1 bit)

Jump to

Block Diagram

CNN Plus IP Compact Mode Block Diagram

CNN Plus IP High Performance Mode Block Diagram

Ordering Information

Multi-Site
Family Part Number
Single Design Multi-Site Subscription
CertusPro-NX CNNPLUS-ACCEL-CPNX-U CNNPLUS-ACCEL-CPNX-UT CNNPLUS-ACCEL-CPNX-US
Certus-NX CNNPLUS-ACCEL-CTNX-U CNNPLUS-ACCEL-CTNX-UT CNNPLUS-ACCEL-CTNX-Us
CrossLink-NX CNNPLUS-ACCEL-CNX-U CNNPLUS-ACCEL-CNX-UT CNNPLUS-ACCEL-CNX-US

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
CNN Plus Accelerator IP User Guide
FPGA-IPUG-02115 1.3 11/10/2021 PDF 1.2 MB

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