RGMII to GMII Bridge Reference Design

Bi-directional bridge function for transferring data between RGMII and GMII

Related Products

Related Applications

GMII (Gigabit Media Independent Interface) is an Ethernet interface standard, and RGMII (Reduced Gigabit Media Independent Interface) is intended to be an alternative to GMII. The principle objective of RGMII is to reduce the number of pins from 22 to 12 in a cost-effective and technology-independent manner. This reference design provides a bi-directional bridge function for transferring data between RGMII and GMII.

Features

  • Data bridging from GMII to RGMII
  • Data bridging from RGMII to GMII
  • Works at >125 MHz
  • Uses the HSTL I/O with no additional HSTL buffers required

Jump to

Block Diagram

RGMII to GMII Bridge Reference Design

Performance and Size

Device Family Language Speed Grade Utilization (LUTs) fMAX (MHz) I/O Architecure
Resources
ECP51 Verilog -8 4 >125 33 2 PLLs, 5 ODDR
LatticeECP32 Verilog -7 4 >125 33 2 PLLs, 5 ODDR
LatticeECP /
LatticeECTM3		 Verilog -4 3 >125 33 2 PLLs, 5 ODDR
LatticeECP / TM4 Verilog -4 3 >125 33 2 PLLs, 5 ODDR
CertusPro-NX5 Verilog -9 4 >125 33 2 PLLs, 5 ODDR
MachXO5-NX6 Verilog -9 4 >125 33 2 PLLs, 5 ODDR

1. Performance and utilization characteristics are generated using LFE5UM-85F-8BG756C, with Lattice Diamond 3.8 design software with LSE (Lattice Synthesis Engine).
2. Performance and utilization characteristics are generated using LFE3-95EA-7FN1156C, with Lattice Diamond 3.8 design software.
3. Performance and utilization characteristics are generated using LFEC20E-4F672C, with Lattice Diamond 3.8 design software.
4. Performance and utilization characteristics are generated using LFXP10E-4F256C, with Lattice Diamond 3.8 design software.
5. Performance and utilization characteristics are generated using LFCPNX-100-7BBG484I, with Lattice Radiant™ 3.1 design software with LSE (Lattice Synthesis Engine).
6. Performance and utilization characteristics are generated using LFMXO5-65T-9BBG484C, with Lattice Radiant 2024.2 design software with LSE (Lattice Synthesis Engine).

Note: The Maximum Clock Frequency is obtained by running the timing analysis with the Lattice design software. Timing simulation should be run after any changes are made and the reference design is merged with the overall design.

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
RGMII to GMII Bridge Reference Design - User Guide
FPGA-RD-02136 2.6 7/15/2025 PDF 257.7 KB
RGMII to GMII Bridge - Source Code
7/15/2025 ZIP 382.7 KB

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