Certus-N2

High Performance General Purpose Small FPGA

Related Products

Related Applications

The Lattice Certus-N2 family of small, general purpose FPGAs deliver up to 220k System Logic Cells of density and up to 8 – 16G multi-protocol SerDes and offer small package options. Built using the Lattice Nexus 2 platform – the family is optimized for low power relative to the competition and supports industry-leading design security in its class.

Improved Performance – 2X more logic density, SerDes speed, and DSP to logic ratio than previous generation

Fast External Memory Support – LPDDR4/DDR4 up to 2400 Mbps

Low Power – Up to 3x lower power than competitive products

Features

  • Up to 8 SerDes channels operating up to 128 Gbps total bandwidth
  • Packages as small as 9x9 mm2 with SerDes, and in ball-pitch options of 0.5, 0.8, and 1.0 mm
  • FPGA fabric features up to 220k System Logic Cells, 12 Mb embedded memory, and 520 – 18 x 18 multipliers
  • Instant-on: < 20 ms configuration using xSPI flash memory
  • Class leading bitstream encryption and authentication

Jump to

Family Table

Certus-N2 Device Selection Guide
Features CT06 CT10 CT16 CT20
System Logic Cells (k) 65 100 160 220
Look-Up-Tables (k LUTs) 40 61 98 135
Embedded Memory (EBR) Blocks (36 kb) 114 153 228 306
Embedded Memory (Mb) 4 5.5 8 12
Distributed RAM Bits (kb) 416 636 1041 1272
DSP (18x18 Multipliers) 120 240 360 520
High Frequency Oscillator (400 MHz) 1 1 1 1
GPLL 4 4 7 7
External Memory Interface support LPDDR4/DDR4
Max 16G SerDes Channels 4 4 8 8
Temperature Grades1 C, I C, I C, I C, I
Bitstream Encryption / Authentication AES-GCM / ECDSA / RSA
0.5 mm Total I/O (Wide Range / High Performance) / SerDes

CT06 CT10 CT16 CT20
ASG187 (FOWLP, 6 × 9.5 mm, 0.5 mm) 87 (27,60) 87 (27,60) — —
ASG273 (FOWLP, 9 × 9 mm, 0.5 mm) 112 (27, 85) / 4 112 (27, 85) / 4 — —
ASG410 (FOWLP, 11 × 9 mm, 0.5 mm) — — 247 (94,153) 247 (94,153)
— — 196 (43, 153) / 4 196 (43, 153) / 4
0.8 mm Total I/O (Wide Range / High Performance) / SerDes

CT06 CT10 CT16 CT20
CBG256 (FCCSP , 14 × 14 mm, 0.8 mm) 153 (51, 102) / 2 153 (51, 102) / 2 — —
CBG484 (FCCSP, 18 × 18 mm, 0.8 mm) 196 (94, 102) / 4 196 (94, 102) / 4 247(94,153) / 4 247(94,153) / 4
1.0 mm Total I/O (Wide Range / High Performance) / SerDes

CT06 CT10 CT16 CT20
LFG672 (FCBGA, 27 × 27 mm, 1.0 mm) — — 349 (94, 255) / 8 349 (94, 255) / 8

1. C=Commercial, I=Industrial

Example Solutions

Industrial Machine Vision Block DiagramExpand Image

Industrial Machine Vision

  • Sensor Interface - MIPI CSI-2, LVDS, SubLVDS
  • Customizable ISP for image processing
  • High BW 10GbE connectivity for streaming lossless quality video
Automotive Zonal Controller / Gateway Block DiagramExpand Image

Automotive Zonal Controller / Gateway

  • Interface bridging and low latency switching
  • Flexible Ethernet, sensor / actuator port configuration
  • Optional image data compression to optimize bandwidth and reduce latency
Frame Grabber Block DiagramExpand Image

Frame Grabber

  • Image acquisition, pre-processing, compression (optional) and DMA over PCIe to host PC
  • SerDes supporting 10GbE video in and PCIe out
  • LPDDR4 external memory support for optional frame buffering

Design Resources

Development Kits & Boards

Our development boards & kits help streamline your design process

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Software

Complete Design Flows, High Ease of Use

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
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Lattice Nexus 2 Platform Data Sheet - Specifications
FPGA-DS-02121 0.71 12/10/2024 PDF 1.8 MB
Lattice Nexus 2 Platform - Overview Data Sheet
FPGA-DS-02122 0.71 12/10/2024 PDF 812.1 KB
Lattice Nexus 2 sysCLOCK PLL Design and User Guide
FPGA-TN-02364 0.81 12/10/2024 PDF 1 MB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 2.6 12/10/2024 PDF 560.4 KB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 5.6 12/10/2024 PDF 6.2 MB
Thermal Management
FPGA-TN-02044 5.4 12/10/2024 PDF 1018.3 KB
Using TraceID
FPGA-TN-02084 2.7 12/10/2024 PDF 408 KB
Lattice Nexus 2 Power User Guide
FPGA-TN-02381 0.80 12/10/2024 PDF 352.4 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Lattice Nexus 2 Platform Data Sheet - Specifications
FPGA-DS-02121 0.71 12/10/2024 PDF 1.8 MB
Lattice Nexus 2 Package Diagram
FPGA-DS-02124 0.81 12/10/2024 ZIP 105.6 KB
Lattice Nexus 2 Platform - Overview Data Sheet
FPGA-DS-02122 0.71 12/10/2024 PDF 812.1 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Lattice Nexus 2 sysCONFIG User Guide
FPGA-TN-02370 0.81 12/10/2024 PDF 3.2 MB
Lattice Nexus 2 Hardware Checklist
FPGA-TN-02317 0.81 12/10/2024 PDF 798.5 KB
Lattice Nexus 2 sysDSP User Guide
FPGA-TN-02362 0.81 12/10/2024 PDF 710 KB
Lattice Nexus 2 sysI/O User Guide
FPGA-TN-02365 0.81 12/10/2024 PDF 647.8 KB
Lattice Nexus 2 High-Speed I/O and External Memory Interface User Guide
FPGA-TN-02372 0.81 12/10/2024 PDF 1.5 MB
Lattice Nexus 2 sysCLOCK PLL Design and User Guide
FPGA-TN-02364 0.81 12/10/2024 PDF 1 MB
Lattice Nexus 2 Embedded Memory User Guide
FPGA-TN-02366 0.81 12/10/2024 PDF 1.1 MB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 2.6 12/10/2024 PDF 560.4 KB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-02041 5.0 12/10/2024 PDF 568.4 KB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 5.6 12/10/2024 PDF 6.2 MB
Thermal Management
FPGA-TN-02044 5.4 12/10/2024 PDF 1018.3 KB
Using TraceID
FPGA-TN-02084 2.7 12/10/2024 PDF 408 KB
Lattice Nexus 2 SED/SEC User Guide
FPGA-TN-02380 0.80 12/10/2024 PDF 311.3 KB
Lattice Nexus 2 Power User Guide
FPGA-TN-02381 0.80 12/10/2024 PDF 352.4 KB
Lattice Nexus 2 Multi-Boot User Guide
FPGA-TN-02385 0.80 12/10/2024 PDF 366.5 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Certus-N2 CT20 CBGG484 Pinout Table
FPGA-SC-02063 0.82 12/10/2024 CSV 23.6 KB
Certus-N2 CT20E ASG410 Pinout Table
FPGA-SC-02078 0.72 12/10/2024 CSV 23.2 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Lattice OrCAD Capture Schematic Library (OLB)
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs. 		FPGA-SC-02005 8.4 12/10/2024 ZIP 2.7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Product Selector Guide
I0211 48.0 12/10/2024 PDF 13.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Lattice Nexus™ 2 Platform: Low Power, High Performance Small FPGA
WP0040 1.0 12/10/2024 PDF 759.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Certus-N2 CT20 BSDL Model file
FPGA-MD-02084 0.8 12/10/2024 ZIP 19.1 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Lattice Nexus 2 Delphi Models
FPGA-MD-02075 0.81 12/5/2024 ZIP 17.5 KB

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