Space Solutions

Advancing the future of commercial space systems with Lattice FPGAs

Related Products

With the rapid growth of low-earth orbit satellites, the space industry is undergoing an unprecedented expansion to offer new capabilities and services. Lattice leverages the experience to build power efficient, small form factor and reliable FPGAs to deliver a scalable portfolio of inherently radiation tolerant FPGAs in support of the emerging field of small satellites for governments and businesses worldwide.

Lattice strives to provide the most reliable FPGAs for space and other harsh environment applications. Lattice NEXUS FPGA reliability and quality have been independently verified by multiple agencies in the United States and Europe to meet the performance, reliability and lifecycle demands of space systems by taking advantage of the following results:

  • Immunity to single event latch-up, tested to high LET
  • High Total Ionizing Dose Immunity
  • Instant-on feature configures I/O in under 4ms with full FPGA configured in less than 30ms
  • Interleaved SRAM memory architecture with no Multiple-Bit Upsets detected

In addition to characterizing radiation effects in reconfigurable FPGAs, Lattice offers mitigation techniques including built-in error detection and correction as well as Triple Modular Redundancy.

Working with a wide array of developers and subject matter experts, Lattice participates in an open radiation test consortium to facilitate industry cooperation, accelerate the development of test platforms and enable public awareness and access to test results. To learn more about how to join the consortium and obtain radiation test reports and other relevant documents, contact Lattice sales.

  • Flexibility to enable in-flight reprogrammable systems coupled with low power operation gives satellite operators the ability to improve mission responsiveness and real-time processing.
  • Lowest soft error rate (SER) in its class and highest latch-up immunity coupled with built-in scrubber to maximize integrity of space systems.
  • Commercial-off-the-shelf (COTS) plastic components speed up prototype build and maintain same design for flight.
  • Low latency, deterministic instant-on combined with superior size, weight, and power specifications to ensure successful missions.

Solving Satellite Systems Architectural Bottlenecks

For more information about obtaining flight tested FPGAs, visit Frontgrade Technologies.

For a complete list of fault tolerant IP cores targeting Lattice FPGAs, visit Lattice Solutions page.

Jump to

Example Applications

Sensor Control

  • Bridge processor to sensors for distributed architectures
  • Small packages and soft RISC-V Cores for control / management
  • Embedded ADC and DAC blocks to simplify design and test

Telemetry

  • Instant-on performance enable fast response and boot time requirements
  • In-orbit reconfiguration to future proof your design
  • Large on-chip memory for on-chip processing and storage

Data Acquisition

  • Digital Signal Processing to offload SBC and accelerate complex functions
  • High speed Serdes simplifies design and supports multiple protocols
  • Vision interface and signal processing adapts to a variety of sensors

Reference Designs

Object Classification Reference Design

Reference Design

Object Classification Reference Design

The Object Classification reference design shows examples on implementing machine-learning based object classification to edge devices applications.
Object Classification Reference Design
Sensor Interfacing and Preprocessing

Reference Design

Sensor Interfacing and Preprocessing

Aggregates data from multiple I2C interfaces and performs preprocessing like buffering, timestamping and complex event triggering based on data analysis.
Sensor Interfacing and Preprocessing
SPI Slave to PWM Generation Reference Design

Reference Design

SPI Slave to PWM Generation Reference Design

Sets the frequency and duty cycle of a PWM (Pulse-Width Modulator) using data from an external SPI master.
SPI Slave to PWM Generation Reference Design
ADC Interface

Reference Design

ADC Interface

Interfaces with the Texas Instruments (TI) ADS64XX family of ADCs via LatticeECP3 FPGA high-speed LVDS I/O
ADC Interface
ECC Module Reference Design

Reference Design

ECC Module Reference Design

Provides Single Error Correction - Double Error Detection (SECDED) capability based on a class of optimal minimum oddweight error parity codes
ECC Module Reference Design

Demos

Object Classification Demonstration

Demo

Object Classification Demonstration

This object classification demo provides a sample application for detecting, classifying, and tracking multiple objects running on CertusPro-NX FPGA.
Object Classification Demonstration
Lattice Image Signal Processing Demo

Demo

Lattice Image Signal Processing Demo

Provides a complete ISP example design on the Lattice ECP5 FPGA for the Embedded Vision Development Kit, ideal for Industrial, Medical, and Automotive applications.
Lattice Image Signal Processing Demo

IP Cores

CSI-2/DSI D-PHY Transmitter IP Core

IP Core

CSI-2/DSI D-PHY Transmitter IP Core

The CSI-2/DSI D-PHY Transmitter Submodule IP is for applications requiring D-PHY transmitter in the FPGA logic & supports both high-speed & low power modes
CSI-2/DSI D-PHY Transmitter IP Core
UART 16550 IP Core

IP Core

UART 16550 IP Core

​​Lattice UART16550 IP Core is designed for use in serial communication, supporting the RS-232, RS-422, RS-485, and Electronic Industries Association (EIA) standards, among others.​
UART 16550 IP Core
GRHSSL - High Speed Serial Link Controller IP Core

IP Core

GRHSSL - High Speed Serial Link Controller IP Core

The GRHSSL IP is a highly configurable high-speed serial link controller, described in VHDL. It can implement a SpaceFibre controller, a WizardLink controller or both.
GRHSSL - High Speed Serial Link Controller IP Core
GRPCI IP Core

IP Core

GRPCI IP Core

The GRPCI IP core provides a 32-bit master/target interface for AMBA AHB 2.0 systems. It includes parameterizable FIFOs for both master and target operation and can optionally be provided with an independent DMA engine.
GRPCI IP Core

Development Kits & Boards

CertusPro-NX Voice and Vision Machine Learning Board

Board

CertusPro-NX Voice and Vision Machine Learning Board

Design AI use cases for the Edge quickly! This board along with the Lattice sensAI solution stack provide the tools for developing vision and audio-based AI applications.
CertusPro-NX Voice and Vision Machine Learning Board

Documention

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices
FPGA-TN-02257 1.1 5/31/2022 PDF 1 MB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 1.8 2/28/2024 PDF 1 MB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-02041 4.8 9/26/2023 PDF 399.4 KB
Thermal Management
FPGA-TN-02044 4.9 3/7/2024 PDF 1.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices
FPGA-TN-02257 1.1 5/31/2022 PDF 1 MB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 1.8 2/28/2024 PDF 1 MB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-02041 4.8 9/26/2023 PDF 399.4 KB
Thermal Management
FPGA-TN-02044 4.9 3/7/2024 PDF 1.1 MB

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