莱迪思解决方案

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  • FFT 编译器

    IP Core

    FFT 编译器

    The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.
    FFT 编译器
  • FIR 滤波器生成器

    IP Core

    FIR 滤波器生成器

    可灵活配置的多通道FIR滤波器。最多支持256个通道,每个拥有2048个抽头。输入和系数宽度为4至32位。
    FIR 滤波器生成器
  • JESD204B IP核

    IP Core

    JESD204B IP核

    莱迪思JESD204B IP核是用于数据转换器和FPGA器件之间的高速串行接口,用于取代传统接口。
    JESD204B IP核
  • PCI Express x1、x4 Root Complex Lite IP核

    IP Core

    PCI Express x1、x4 Root Complex Lite IP核

    Provides a PCI Express x1 and x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCIe protocol stack
    PCI Express x1、x4 Root Complex Lite IP核
  • AXI4 to APB Bridge Module

    IP Core

    AXI4 to APB Bridge Module

    The Lattice Semiconductor AXI4 to APB Bridge Module provides an interface between the high-speed AXI4 and APB.
    AXI4 to APB Bridge Module
  • AXI4 to AHB-Lite Bridge Module IP Core

    IP Core

    AXI4 to AHB-Lite Bridge Module IP Core

    Lattice Semiconductor AXI4 to AHB-Lite Bridge Module provides an interface between the high-speed AXI4 and AHB-Lite.
    AXI4 to AHB-Lite Bridge Module IP Core
  • AHB-Lite to AXI4 Bridge Module IP Core

    IP Core

    AHB-Lite to AXI4 Bridge Module IP Core

    The Lattice AHB-Lite to AXI4 Bridge IP Core is used for interfacing one AHB-Lite Manager and one AXI4 Subordinate.
    AHB-Lite to AXI4 Bridge Module IP Core
  • AXI4 Interconnect IP Core

    IP Core

    AXI4 Interconnect IP Core

    AXI4 Interconnect is a flexible, versatile, and easy-to-use IP with high-performance and low-latency interconnect fabric for AMBA 4 AXI/AXI-lite based systems.
    AXI4 Interconnect IP Core
  • Helion IONOS图像信号处理IP系列

    IP Core

    Helion IONOS图像信号处理IP系列

    来自Helion Vision的全面、高质量、可自行配置的ISP解决方案,包括了从基本到高级的高动态范围成像(HDRI)色彩流水线。
    Helion IONOS图像信号处理IP系列
  • AXI Register Slice IP Core

    IP Core

    AXI Register Slice IP Core

    The AXI Register Slice connects the AXI subordinate to the AXI manager by introducing pipeline stages in between to close the timing in critical paths.
    AXI Register Slice IP Core
  • 三倍速以太网MAC

    IP Core

    三倍速以太网MAC

    在主机处理器和以太网之间发送和接收数据。符合IEEE 802.3标准。支持10/100/1000 Mbps传输速率。
    三倍速以太网MAC
  • I2C从动软核

    Reference Design

    I2C从动软核

    使用Verilog实现软核I2C从动,支持多款莱迪思FPGA系列
    I2C从动软核
  • I2C总线主控软核

    Reference Design

    I2C总线主控软核

    使用Verilog实现软核I2C总线主控,支持多款莱迪思FPGA系列
    I2C总线主控软核
  • Generic Soft SPI Master Controller Demonstration

    演示

    Generic Soft SPI Master Controller Demonstration

    This demo implements the Generic Soft SPI Master Controller Reference Design by performing simple transactions to the external SPI Flash device found in the MachXO3-9400 Development Board
    Generic Soft SPI Master Controller Demonstration
  • I2C (Inter-Integrated Circuit) 主控- WISHBONE兼容

    Reference Design

  • I2C总线主控

    Reference Design

    I2C总线主控

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    I2C总线主控
  • DDR3 SDRAM控制器

    IP Core

    DDR3 SDRAM控制器

    通用存储器控制器可连接行业标准的DDR3存储器(JESD79-3标准),并提供通用指令接口
    DDR3 SDRAM控制器
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