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  • 5G Small Cell PCIe to JESD204B Bridge Reference Design

    Reference Design

    5G Small Cell PCIe to JESD204B Bridge Reference Design

    5G Mid-Power Integrated Small Cell, reference platform is a comprehensive development board tailored for 5G baseband processors and transceiver frontends.
    5G Small Cell PCIe to JESD204B Bridge Reference Design
  • Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP

    Demo

    Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP

    Demo for Lattice ORAN Secure Sync show how Lattice FPGA w/ soft IPs can support tight & secure synchronization using 1588 PTP & ITU profiles for Telecom.
    Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP
  • Lattice ORAN Timing and Synchronization Kit

    Board

    Lattice ORAN Timing and Synchronization Kit

    ORAN Sync Board has 2x 10GE & 2x 1GE ports, SMA & FMC connectors for testing, demos, development, GNSS & on-board timing sources, ToD, & PPS RJ48 connectors
    Lattice ORAN Timing and Synchronization Kit
  • Lattice ORAN™ 1.0 Security Reference Design

    Reference Design

    Lattice ORAN™ 1.0 Security Reference Design

    Lattice ORAN enable secure out-of-band communication over I3C/SMBus/I2C/PCIe and provide crypto-256 and Crypto-384 services to customers through software APIs.
    Lattice ORAN™ 1.0 Security Reference Design
  • Lattice ORAN™ Control Demonstration

    Demo

    Lattice ORAN™ Control Demonstration

    Lattice ORAN provides packet authentication, encryption and decryption and support SPDM protocol over MCTP.
    Lattice ORAN™ Control Demonstration
  • I3C Controller IP Core

    IP Core

    I3C Controller IP Core

    I3C Controller IP Core is a two-wire, bi-directional serial bus designed for use with many sensor secondary devices controlled by a single I3C controller.
    I3C Controller IP Core
  • I3C Target IP Core

    IP Core

    I3C Target IP Core

    I3C Target IP Core enables greater than 10-fold speed improvements, more effective bus power management, and backward compatibility with I2C devices.
    I3C Target IP Core
  • Soft I2C Bus Master

    Reference Design

    Soft I2C Bus Master

    Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families
    Soft I2C Bus Master
  • Soft I2C Slave Peripheral

    Reference Design

    Soft I2C Slave Peripheral

    Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families
    Soft I2C Slave Peripheral
  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    I2C Bus Master
  • I2C Master - WISHBONE Compatible

    Reference Design

    I2C Master - WISHBONE Compatible

    Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus
    I2C Master - WISHBONE Compatible
  • UART Reference Design - WISHBONE Compatible

    Reference Design

    UART Reference Design - WISHBONE Compatible

    UART (Universal Asynchronous Receiver/Transmitter) provides both Rx and Tx between the WISHBONE system bus and an RS232 serial communication channel.
    UART Reference Design - WISHBONE Compatible
  • Power Sequencing with Fault Logging Demo

    Demo

    Power Sequencing with Fault Logging Demo

    Uses L-ASC10 to monitor, sequence four separate Power Planes from a central control point. Logs faults with timestamps. Expandable.
    Power Sequencing with Fault Logging Demo
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