I3C Controller IP Core

Supports Several Communication Formats - All Sharing a Two-wire Interface

Related Products

Related Applications


Newsletter Subscription

The Lattice I3C IP Core is designed to comply with the MIPI I3C specification. An I3C bus requires exactly one I3C device at a time functioning as an I3C Controller device. In I3C terms, this I3C Controller device is the active Controller at that time.

I3C Controller IP supports several communication formats, all sharing a two-wire interface: SDA bidirectional data line and SCL bidirectional clock. The Lattice I3C Controller supports the following modes:

  • SDR mode
  • HDR-DDR mode

Resource Utilization details are available in the IP Core User Guide.

Features

  • Compatible with MIPI I3C Specification v1.1.1
  • Two wire serial interface up to 12.5 MHz using Push-Pull
  • Legacy I2C device coexist on the same bus (with some limitations)
  • Dynamic Addressing while supporting Static Addressing for legacy I2C devices
  • I2C-like SDR messaging

Block Diagram

I3C Controller Block DiagramExpand Image

Resource Utilization

LFCPNX-100-7ASG256C
Configuration Registers LUTs EBRs DSPs
Default 437 1268 2 0
IBI Capable = True
Hot-Join Capable = True		 497 1417 2 0
IBI Capable = True
Hot-Join Capable = True
SCL Pulse Width = 16
Open-Drain Pulse Width = 4		 497 1424 2 0
IBI Capable = True
Hot-Join Capable = False
SCL Pulse Width = 128
Open-Drain Pulse Width = 16		 494 1400 2 0

1. Fmax is generated when the FPGA design only contains the SDR module, and the target frequency is 200 MHz. These values may be reduced when user logic is added to the FPGA design.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.

LIFCL-40-7BG256I
Configuration Registers LUTs EBRs DSPs
Default 437 1268 2 0
IBI Capable = True
Hot-Join Capable = True		 497 1417 2 0
IBI Capable = True
Hot-Join Capable = True
SCL Pulse Width = 16
Open-Drain Pulse Width = 4		 497 1424 2 0
IBI Capable = True
Hot-Join Capable = False
SCL Pulse Width = 128
Open-Drain Pulse Width = 16		 494 1400 2 0

1. Fmax is generated when the FPGA design only contains the SDR module, and the target frequency is 200 MHz. These values may be reduced when user logic is added to the FPGA design.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
Avant-G I3C-M-AVG-UT I3C-M-AVG-US
Avant-X I3C-M-AVX-UT I3C-M-AVX-US
Avant-E I3C-M-AVE-UT I3C-M-AVE-US
MachXO5-NX I3C-M-XO5-UT I3C-M-XO5-US
CertusPro-NX I3C-M-CPNX-UT I3C-M-CPNX-US
CrossLink-NX I3C-M-CNX-UT I3C-M-CNX-US
Certus-NX I3C-M-CNX-UT I3C-M-CNX-US
iCE40 UltraPlus I3C-M-UP-UT I3C-M-UP-US
Bundled MIPI-BNDL-UT MIPI-BNDL-US

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

Purchase: To find out how to purchase the IP Core, please contact your local Lattice distributor or sales representative.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
I3C Controller Driver API Reference
FPGA-TN-02342 1.0 12/21/2023 PDF 894.8 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
I3C Controller Driver API Reference
FPGA-TN-02342 1.0 12/21/2023 PDF 894.8 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
I3C Controller IP Core - User Guide
FPGA-IPUG-02228 1.3 6/28/2024 PDF 2.1 MB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

ABOUT LATTICE

SALES

SUPPORT

FOLLOW