5G Open RAN

The Advent of 5G ushers in a new era of ultra-large scale connectivity to accommodate IoT, significant bandwidth increases to meet the exponential growth of social media, streaming and gaming services, and low latency support for delay sensitive applications such as autonomous vehicle control and commercial drone applications.

To satisfy all of the use cases, more sophisticated design architectures are deployed within the Radio Unit (RU) and Distribution Unit (DU) .This, in turn, results in the need to manage more components on control paths and attention to power and thermal requirements of the system is critical.

In addition, board security is an important consideration as carriers are increasingly scrutinizing the integrity of equipment to defend against malicious attacks designed to incapacitate the network.

Lattice FPGA solutions provide:

  • Highly scalable PLD solution to meet all control needs
  • Best-in-Class security solutions to ensure protection of all boot functions and devices
  • Programmable to accommodate evolving 5G standards in the control plane

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Example Use Cases

O-RAN Split 7.2: RU Hardware Management Use Case

  • Precision power management and sequencing
  • Accurate temperature monitoring
  • Fault logging to efficiently identify HW faults
  • Reduced routing congestion and BOM

O-RAN Split 7.2: DU Platform Security Use Case

  • Protection for all firmware and critical data on board
  • Cryptography detect corrupted platform firmware at power on and all systems updates
  • Recover corrupted firmware and critical data to known good state

5G RAN DU Polar Code Use Case

  • Compliant with 3GPP 5G TS 38212 V15.7.0
  • Support for successive cancelation algorithm
  • Support for Code block lengths of 32,64,128, 256,512 and 1024
  • Support CRC6, CRC11, CRC24

Reference Designs

5G Small Cell PCIe to JESD204B Bridge Reference Design

Reference Design

5G Small Cell PCIe to JESD204B Bridge Reference Design

5G Mid-Power Integrated Small Cell, reference platform is a comprehensive development board tailored for 5G baseband processors and transceiver frontends.
5G Small Cell PCIe to JESD204B Bridge Reference Design
Lattice ORAN™ 1.0 Security Reference Design

Reference Design

Lattice ORAN™ 1.0 Security Reference Design

Lattice ORAN enable secure out-of-band communication over I3C/SMBus/I2C/PCIe and provide crypto-256 and Crypto-384 services to customers through software APIs.
Lattice ORAN™ 1.0 Security Reference Design
Soft I2C Bus Master

Reference Design

Soft I2C Bus Master

Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families
Soft I2C Bus Master
Soft I2C Slave Peripheral

Reference Design

Soft I2C Slave Peripheral

Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families
Soft I2C Slave Peripheral
I2C Bus Master

Reference Design

I2C Bus Master

Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
I2C Bus Master

IP Cores

I3C Controller IP Core

IP Core

I3C Controller IP Core

I3C Controller IP Core is a two-wire, bi-directional serial bus designed for use with many sensor secondary devices controlled by a single I3C controller.
I3C Controller IP Core
I3C Target IP Core

IP Core

I3C Target IP Core

I3C Target IP Core enables greater than 10-fold speed improvements, more effective bus power management, and backward compatibility with I2C devices.
I3C Target IP Core

Demo

Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP

Demo

Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP

Demo for Lattice ORAN Secure Sync show how Lattice FPGA w/ soft IPs can support tight & secure synchronization using 1588 PTP & ITU profiles for Telecom.
Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP
Lattice ORAN™ Control Demonstration

Demo

Lattice ORAN™ Control Demonstration

Lattice ORAN provides packet authentication, encryption and decryption and support SPDM protocol over MCTP.
Lattice ORAN™ Control Demonstration
Power Sequencing with Fault Logging Demo

Demo

Power Sequencing with Fault Logging Demo

Uses L-ASC10 to monitor, sequence four separate Power Planes from a central control point. Logs faults with timestamps. Expandable.
Power Sequencing with Fault Logging Demo

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