5G Open RAN

The Advent of 5G ushers in a new era of ultra-large scale connectivity to accommodate IoT, significant bandwidth increases to meet the exponential growth of social media, streaming and gaming services, and low latency support for delay sensitive applications such as autonomous vehicle control and commercial drone applications.

To satisfy all of the use cases, more sophisticated design architectures are deployed within the Radio Unit (RU) and Distribution Unit (DU) .This, in turn, results in the need to manage more components on control paths and attention to power and thermal requirements of the system is critical.

In addition, board security is an important consideration as carriers are increasingly scrutinizing the integrity of equipment to defend against malicious attacks designed to incapacitate the network.

Lattice FPGA solutions provide:

  • Highly scalable PLD solution to meet all control needs
  • Best-in-Class security solutions to ensure protection of all boot functions and devices
  • Programmable to accommodate evolving 5G standards in the control plane

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Example Use Cases

O-RAN Split 7.2: RU Hardware Management Use Case

  • Precision power management and sequencing
  • Accurate temperature monitoring
  • Fault logging to efficiently identify HW faults
  • Reduced routing congestion and BOM

O-RAN Split 7.2: DU Platform Security Use Case

  • Protection for all firmware and critical data on board
  • Cryptography detect corrupted platform firmware at power on and all systems updates
  • Recover corrupted firmware and critical data to known good state

5G RAN DU Polar Code Use Case

  • Compliant with 3GPP 5G TS 38212 V15.7.0
  • Support for successive cancelation algorithm
  • Support for Code block lengths of 32,64,128, 256,512 and 1024
  • Support CRC6, CRC11, CRC24

Reference Designs

Soft I2C Bus Master

Reference Design

Soft I2C Bus Master

Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families
Soft I2C Bus Master
Soft I2C Bus Master

Reference Design

Soft I2C Bus Master

Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families
Soft I2C Bus Master
Soft I2C Slave Peripheral

Reference Design

Soft I2C Slave Peripheral

Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families
Soft I2C Slave Peripheral
Soft I2C Slave Peripheral

Reference Design

Soft I2C Slave Peripheral

Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families
Soft I2C Slave Peripheral
I2C Bus Master

Reference Design

I2C Bus Master

Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
I2C Bus Master

IP Cores

I3C Master IP Core

IP Core

I3C Master IP Core

Bus controller following the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
I3C Master IP Core
I3C Master IP Core

IP Core

I3C Master IP Core

Bus controller following the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
I3C Master IP Core
I3C Slave IP Core

IP Core

I3C Slave IP Core

Interfaces to the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
I3C Slave IP Core
I3C Slave IP Core

IP Core

I3C Slave IP Core

Interfaces to the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
I3C Slave IP Core

Demo

Power Sequencing with Fault Logging Demo

Demo

Power Sequencing with Fault Logging Demo

Uses L-ASC10 to monitor, sequence four separate Power Planes from a central control point. Logs faults with timestamps. Expandable.
Power Sequencing with Fault Logging Demo
Power Sequencing with Fault Logging Demo

Demo

Power Sequencing with Fault Logging Demo

Uses L-ASC10 to monitor, sequence four separate Power Planes from a central control point. Logs faults with timestamps. Expandable.
Power Sequencing with Fault Logging Demo

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Quality & Reliability

Reference Material to Help Answer Your Questions

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