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  • CertusPro-NX Versa Board

    Board

    CertusPro-NX Versa Board

    CertusPro-NX Versa Board supports a wide range industry standards such as MIPI, SFP+, 10 GbE, LPDDR4 and PCIe (Gen3) for rapid prototyping and testing.
    CertusPro-NX Versa Board
  • CrossLinkU-NX Evaluation Board

    Board

    CrossLinkU-NX Evaluation Board

    CrossLinkU-NX Evaluation Board is a platform for general purpose application development using CrossLinkU-NX device, the first FPGA with hard USB2/3 (5Gbps) interface.
    CrossLinkU-NX Evaluation Board
  • USB 2.0/3.2 IP Core

    IP Core

    USB 2.0/3.2 IP Core

    Lattice USB 2.0/3.2 IP Core provides a solution to interface with a USB host and can be targeted to the Lattice CrossLink-NX FPGA Devices.
    USB 2.0/3.2 IP Core
  • USB to I/O Aggregation and Bridging Demonstration

    Demo

    USB to I/O Aggregation and Bridging Demonstration

    The USB to I/O Aggregation and Bridging Demo shows the capabilities of the Lattice FPGA and accelerating USB 2.0/3.2 (5Gbps) Interface Innovation.
    USB to I/O Aggregation and Bridging Demonstration
  • USB to I/O Aggregation and Bridging Reference Design

    Reference Design

    USB to I/O Aggregation and Bridging Reference Design

    USB to IO Bridging Reference Design Create plug-and-play peripheral expansion on USB-enabled FPGA & signal protocol conversion from USB to I2C, SPI, & GPIO.
    USB to I/O Aggregation and Bridging Reference Design
  • PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demonstrates the multifunction capabilities of the Crosslink-NX FPGA that allows access to GPIO, MDIO and I2C registers.
    PCIe Multifunction Demo for Lattice Nexus-based FPGAs
  • Lattice Sentry I2C Filter IP Core

    IP Core

    Lattice Sentry I2C Filter IP Core

    Sentry I2C Filter IP Core provides an interface between I2C bus devices and a host processor while protecting against common I2C bus vulnerabilities.
    Lattice Sentry I2C Filter IP Core
  • Lattice Sentry SMBus Mailbox IP Core

    IP Core

    Lattice Sentry SMBus Mailbox IP Core

    SMBus, a two-wire interface that support fairness arbitration and compatible with AHB-Lite specification. Target devices are Mach-NX and MachXO3D.
    Lattice Sentry SMBus Mailbox IP Core
  • Lattice Sentry I2C Monitor IP Core for MachXO3D

    IP Core

    Lattice Sentry I2C Monitor IP Core for MachXO3D

    Propel IP Module for Lattice Sentry: Monitors traffic on I2C bus to identify and block potentially illegal traffic.
    Lattice Sentry I2C Monitor IP Core for MachXO3D
  • Lattice Sentry Root of Trust Reference Design for Mach-NX

    Reference Design

    Lattice Sentry Root of Trust Reference Design for Mach-NX

    This design utilizes Platform Firmware Resiliency System Root of Trust to help develop and test a complete NIST 800-193 compliant security system that protects, detects, and recovers.
    Lattice Sentry Root of Trust Reference Design for Mach-NX
  • MachXO5T-NX Development Board

    Board

    MachXO5T-NX Development Board

    The MachXO5T-NX Development Board offers a variety of features and programmability that enhances Secure Control PLD functionality with Multiple Boot.
    MachXO5T-NX Development Board
  • MachXO5™-NX Development Board

    Board

    MachXO5™-NX Development Board

    Allows designers to work with features of MachXO5-25 and L-ASC10 hardware management expander to assist in rapid prototyping and testing of specific designs
    MachXO5™-NX Development Board
  • MIPI CSI-2 to HDMI Demonstration

    Demo

    MIPI CSI-2 to HDMI Demonstration

    Lattice MIPI-HDMI Demonstration is built using multiple Lattice IPs and some additional glue logic necessary to connect the IPs in a processing pipeline.
    MIPI CSI-2 to HDMI Demonstration
  • MIPI CSI-2 to HDMI Reference Design

    Reference Design

    MIPI CSI-2 to HDMI Reference Design

    MIPI CSI-2 to HDMI Reference Design includes the synthesizable MIPI-HDMI core design & stimulus generators, checkers, & a testbench necessary to simulate the design
    MIPI CSI-2 to HDMI Reference Design
  • LVDS Tunneling Protocol and Interface Reference Design

    Reference Design

    LVDS Tunneling Protocol and Interface Reference Design

    The DC-SCM 2.0 LTPI Reference Design provides multiple solution compliant with DC-SCM 2.0 with a standardized DC-SCI and aggregating multiple data channels.
    LVDS Tunneling Protocol and Interface Reference Design
  • Single Wire Signal Aggregation Demonstration

    Demo

    Single Wire Signal Aggregation Demonstration

    Single Wire Signal Aggregation Demonstration contains two boards to demonstrate the complete working design in a stand-alone configuration.
    Single Wire Signal Aggregation Demonstration
  • I2C to APB Bridge Reference Design

    Reference Design

    I2C to APB Bridge Reference Design

    With support APB read / write capability, the I2C to APB Bridge Reference Design converts external I2C Master into APB Master transaction.
    I2C to APB Bridge Reference Design
  • SubLVDS to MIPI CSI-2 Image Sensor Bridge with CertusPro-NX

    Reference Design

    SubLVDS to MIPI CSI-2 Image Sensor Bridge with CertusPro-NX

    Modular MIPI/D-PHY Reference Design - Solves the mismatch between SubLVDS output image sensor and an ISP/AP using CSI-2 interface.
    SubLVDS to MIPI CSI-2 Image Sensor Bridge with CertusPro-NX
  • Future Electronics Hedgehog Development Board

    Board

    Future Electronics Hedgehog Development Board

    Future Electronics MachXO5-NX breakout board featuring LFMXO5-25-7BBG256C FPGA. Raspberry Pi, Arduino, MikroBus, PMOD, and MIPI camera/display interfaces.
    Future Electronics Hedgehog Development Board
  • SLS I2C Master IP Core

    IP Core

    SLS I2C Master IP Core

    Ease to use I2C Master IP core from SLS. It comes with ready to use HAL driver, reference design and various documents.
    SLS I2C Master IP Core
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