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  • Lattice Sentry I2C Monitor IP Core for MachXO3D

    IP Core

    Lattice Sentry I2C Monitor IP Core for MachXO3D

    Propel IP Module for Lattice Sentry: Monitors traffic on I2C bus to identify and block potentially illegal traffic.
    Lattice Sentry I2C Monitor IP Core for MachXO3D
  • CrossLink-NX PCIe Bridge Board

    Board

    CrossLink-NX PCIe Bridge Board

    Connectivity Development Platform Enabling Bridging of Multi-Standard I/O Interfaces to PCIe
    CrossLink-NX PCIe Bridge Board
  • EFB Module

    IP Core

    EFB Module

    Propel IP Module: Implements the Embedded Function Block (EFB) in MachXO3D, including I2C, Configuration Blocks and User Flash Memory with an APB Interface.
    EFB Module
  • MAS LIFCL Evaluation Board

    Board

    MAS LIFCL Evaluation Board

    This modular, flexible and easy-to-use CrossLink-NX 17 board is designed for video applications, including CSI2 MIPI, LVDS HDMI (through PMOD).
    MAS LIFCL Evaluation Board
  • SDI to MIPI CSI-2 Bridge by Antmicro

    Board

    SDI to MIPI CSI-2 Bridge by Antmicro

    This device using Lattice CrossLink LIF-MD6000-6KMG80I that enables connecting industrial and filmmaking cameras and video accessories to edge AI platforms which often include the MIPI CSI-2 interface.
    SDI to MIPI CSI-2 Bridge by Antmicro
  • Soft I2C Bus Master

    Reference Design

    Soft I2C Bus Master

    Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families
    Soft I2C Bus Master
  • Soft I2C Master and Slave – Simple Write and Read

    Demo

    Soft I2C Master and Slave – Simple Write and Read

    Demonstrates the operation of an I2C Master and Slave doing simple write and read of data.
    Soft I2C Master and Slave – Simple Write and Read
  • Soft I2C Slave Peripheral

    Reference Design

    Soft I2C Slave Peripheral

    Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families
    Soft I2C Slave Peripheral
  •  I2C Slave IP Core

    IP Core

    I2C Slave IP Core

    Interfaces to an I2C bus. Supports 7-bit and 10-bit addressing mode with programmable SCL frequency. Standard, Fast and Fast-mode plus support - up to 1 Mbit/s
     I2C Slave IP Core
  • 3D Depth Mapping

    Demo

    3D Depth Mapping

    Determines the distance between an embedded device and an object using a Semi-Global Block Matching (SGBM) algorithm to determine 64 different disparity levels
    3D Depth Mapping
  • I2C Master IP Core

    IP Core

    I2C Master IP Core

    Controls an I2C bus. Supports 7-bit and 10-bit addressing mode with programmable SCL frequency. Standard, Fast and Fast-mode plus support - up to 1 Mbit/s
    I2C Master IP Core
  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    I2C Bus Master
  • I2C Master - WISHBONE Compatible

    Reference Design

    I2C Master - WISHBONE Compatible

    Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus
    I2C Master - WISHBONE Compatible
  • Infrared Remote Tx/Rx Reference Designs

    Reference Design

    Infrared Remote Tx/Rx Reference Designs

    Implements an interface to IR receive and/or IR transmit. This includes PWM (pulse width modulation) timing and protocol conversion to an SPI /I2C bus
    Infrared Remote Tx/Rx Reference Designs
  • Long Range (LoRa) Wireless

    Reference Design

    Long Range (LoRa) Wireless

    Implement a LoRa compliant device using a tiny iCE40 UltraPlus FPGA, for low-power, low-footprint wireless communication over miles
    Long Range (LoRa) Wireless
  • Graphics Acceleration

    Reference Design

    Graphics Acceleration

    Enables a processor to save power in sleep mode while the low-power iCE40 UltraPlus drives a mobile DSI display, and monitors for wake-up signals.
    Graphics Acceleration
  • Sensor Data Buffer

    Reference Design

    Sensor Data Buffer

    Interfaces between multiple I2C-based sensors and a processor's UART. Saves power and resources by always collecting data, while the processor sleeps.
    Sensor Data Buffer
  • Sensor Interfacing and Preprocessing

    Reference Design

    Sensor Interfacing and Preprocessing

    Aggregates data from multiple I2C interfaces and performs preprocessing like buffering, timestamping and complex event triggering based on data analysis.
    Sensor Interfacing and Preprocessing
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