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  • PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demonstrates the multifunction capabilities of the Crosslink-NX FPGA that allows access to GPIO, MDIO and I2C registers.
    PCIe Multifunction Demo for Lattice Nexus-based FPGAs
  • Lattice Sentry I2C Filter IP Core

    IP Core

    Lattice Sentry I2C Filter IP Core

    SMBus relay with I2C filter and provides 4 interface to protect malicious traffic.
    Lattice Sentry I2C Filter IP Core
  • Lattice Sentry SMBus Mailbox IP Core

    IP Core

    Lattice Sentry SMBus Mailbox IP Core

    SMBus, a two-wire interface that support fairness arbitration and compatible with AHB-Lite specification. Target devices are Mach-NX and MachXO3D.
    Lattice Sentry SMBus Mailbox IP Core
  • Lattice Sentry I2C Monitor IP Core for MachXO3D

    IP Core

    Lattice Sentry I2C Monitor IP Core for MachXO3D

    Propel IP Module for Lattice Sentry: Monitors traffic on I2C bus to identify and block potentially illegal traffic.
    Lattice Sentry I2C Monitor IP Core for MachXO3D
  • Lattice Sentry Root of Trust Reference Design for Mach-NX

    Reference Design

    Lattice Sentry Root of Trust Reference Design for Mach-NX

    This design utilizes Platform Firmware Resiliency System Root of Trust to help develop and test a complete NIST 800-193 compliant security system that protects, detects, and recovers.
    Lattice Sentry Root of Trust Reference Design for Mach-NX
  • MachXO5™-NX Development Board

    Board

    MachXO5™-NX Development Board

    Allows designers to work with features of MachXO5-25 and L-ASC10 hardware management expander to assist in rapid prototyping and testing of specific designs
    MachXO5™-NX Development Board
  • SubLVDS to MIPI CSI-2 Image Sensor Bridge with CertusPro-NX

    Reference Design

    SubLVDS to MIPI CSI-2 Image Sensor Bridge with CertusPro-NX

    Modular MIPI/D-PHY Reference Design - Solves the mismatch between SubLVDS output image sensor and an ISP/AP using CSI-2 interface.
    SubLVDS to MIPI CSI-2 Image Sensor Bridge with CertusPro-NX
  • CrossLink-NX PCIe Bridge Board

    Board

    CrossLink-NX PCIe Bridge Board

    Connectivity Development Platform Enabling Bridging of Multi-Standard I/O Interfaces to PCIe
    CrossLink-NX PCIe Bridge Board
  • EFB Module

    IP Core

    EFB Module

    Propel IP Module: Implements the Embedded Function Block (EFB) in MachXO3D, including I2C, Configuration Blocks and User Flash Memory with an APB Interface.
    EFB Module
  • MachXO2ZE Breakout Board

    Board

    MachXO2ZE Breakout Board

    MachXO2ZE Breakout Board, a development board that uses a powerful FPGA with embedded system security to help you design and innovate your next great idea or product.
    MachXO2ZE Breakout Board
  • MAS LIFCL Evaluation Board

    Board

    MAS LIFCL Evaluation Board

    This modular, flexible and easy-to-use CrossLink-NX 17 board is designed for video applications, including CSI2 MIPI, LVDS HDMI (through PMOD).
    MAS LIFCL Evaluation Board
  • SDI to MIPI CSI-2 Bridge by Antmicro

    Board

    SDI to MIPI CSI-2 Bridge by Antmicro

    This device using Lattice CrossLink LIF-MD6000-6KMG80I that enables connecting industrial and filmmaking cameras and video accessories to edge AI platforms which often include the MIPI CSI-2 interface.
    SDI to MIPI CSI-2 Bridge by Antmicro
  • Soft I2C Bus Master

    Reference Design

    Soft I2C Bus Master

    Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families
    Soft I2C Bus Master
  • Soft I2C Master and Slave – Simple Write and Read

    Demo

    Soft I2C Master and Slave – Simple Write and Read

    Demonstrates the operation of an I2C Master and Slave doing simple write and read of data.
    Soft I2C Master and Slave – Simple Write and Read
  • Soft I2C Slave Peripheral

    Reference Design

    Soft I2C Slave Peripheral

    Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families
    Soft I2C Slave Peripheral
  •  I2C Slave IP Core

    IP Core

    I2C Slave IP Core

    Interfaces to an I2C bus. Supports 7-bit and 10-bit addressing mode with programmable SCL frequency. Standard, Fast and Fast-mode plus support - up to 1 Mbit/s
     I2C Slave IP Core
  • 3D Depth Mapping - SGBM Algorithm

    Demo

    3D Depth Mapping - SGBM Algorithm

    Determines the distance between an embedded device and an object using a Semi-Global Block Matching (SGBM) algorithm to determine 64 different disparity levels
    3D Depth Mapping - SGBM Algorithm
  • I2C Master IP Core

    IP Core

    I2C Master IP Core

    Controls an I2C bus. Supports 7-bit and 10-bit addressing mode with programmable SCL frequency. Standard, Fast and Fast-mode plus support - up to 1 Mbit/s
    I2C Master IP Core
  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    I2C Bus Master
  • I2C Master - WISHBONE Compatible

    Reference Design

    I2C Master - WISHBONE Compatible

    Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus
    I2C Master - WISHBONE Compatible
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