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  • PCIe Basic Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Basic Demo for Lattice Nexus-based FPGAs

    The PCIe Basic Demo allows you to control three 7 segment LEDs and manipulate the onboard memory of the FPGA through the PCIe slot.
    PCIe Basic Demo for Lattice Nexus-based FPGAs
  • PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    Demo that displays a series of moving colorbars by streaming the image data using DMA transfers from the FPGA to the host system.
    PCIe Colorbar Demo for Lattice Nexus-based FPGAs
  • PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    The PCI Express DMA Throughput Demo allows to initiate DMA read and write transactions, transferring data from the host to the FPGA and vice versa.
    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs
  • PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demonstrates the multifunction capabilities of the Crosslink-NX FPGA that allows access to GPIO, MDIO and I2C registers.
    PCIe Multifunction Demo for Lattice Nexus-based FPGAs
  • PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    IP Core

    PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express x1 & x4 IP Core for Nexus-based FPGAs
  • Flash Access IP Core

    IP Core

    Flash Access IP Core

    Flash Access IP Core performs write and read access through the LMMI interface.
    Flash Access IP Core
  • I3C Controller IP Core

    IP Core

    I3C Controller IP Core

    I3C Controller IP Core is a two-wire, bi-directional serial bus designed for use with many sensor secondary devices controlled by a single I3C controller.
    I3C Controller IP Core
  • I3C Target IP Core

    IP Core

    I3C Target IP Core

    I3C Target IP Core enables greater than 10-fold speed improvements, more effective bus power management, and backward compatibility with I2C devices.
    I3C Target IP Core
  • MDIO Leader IP Core

    IP Core

    MDIO Leader IP Core

    MDIO LEADER IP features three different standard interfaces for accessing the control and status signals of Leader: APB, AHB-L and AXI-L.
    MDIO Leader IP Core
  • Single Wire Signal Aggregation Demo and Development Board

    Board

    Single Wire Signal Aggregation Demo and Development Board

    Use the world’s smallest form factor FPGAs to aggregate multiple data streams such as I2C, I2S and GPIO in TDM fashion, transmit over single wire, and de-aggregate.
  • Single Wire Signal Aggregation Reference Design

    Reference Design

    Single Wire Signal Aggregation Reference Design

    Use a low-cost FPGA to aggregate multiple data streams such as I2C, UART, I2S and GPIO in TDM fashion, transmit a over single wire, and de-aggregate.
    Single Wire Signal Aggregation Reference Design
  • 8N1 UART Transceiver Reference Design

    Reference Design

    8N1 UART Transceiver Reference Design

    8-bit data, no parity, and 1 stop bit Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel and parallel to serial conversions on data characters received from a peripheral device or CPU
    8N1 UART Transceiver Reference Design
  • Soft I2C Bus Master

    Reference Design

    Soft I2C Bus Master

    Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families
    Soft I2C Bus Master
  • Soft I2C Master and Slave – Simple Write and Read

    Demo

    Soft I2C Master and Slave – Simple Write and Read

    Demonstrates the operation of an I2C Master and Slave doing simple write and read of data.
    Soft I2C Master and Slave – Simple Write and Read
  • Soft I2C Slave Peripheral

    Reference Design

    Soft I2C Slave Peripheral

    Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families
    Soft I2C Slave Peripheral
  • GPIO IP Core

    IP Core

    GPIO IP Core

    Detects and controls GPIOs via Lattice Memory Mapped Interface (LMMI) or Advanced Peripheral Bus Interface (APB).
    GPIO IP Core
  • SPI Master IP Core

    IP Core

    SPI Master IP Core

    Lattice SPI Master IP Core is used to communicate with external SPI slave devices such as display drivers, SPI EPROMS, and analog-to-digital converters.
    SPI Master IP Core
  • SPI Slave IP Core

    IP Core

    SPI Slave IP Core

    The SPI is a high-speed synchronous interface allowing a serial bit stream of configured length to be shifted into and out of the device.
    SPI Slave IP Core
  • I2C Master IP Core

    IP Core

  • I2C Slave IP Core

    IP Core

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