莱迪思解决方案

演示

Crosslink-NX PCIe桥接板上的PCIe基础演示

该PCIe基础演示可以控制三个7段LED，并通过PCIe插槽操作FPGA的片上存储器。

CrossLink-NX, Certus-NX, CertusPro-NX 

SPI, Camera, CSI Camera, Ethernet, PCIe, PMOD, RJ-45, X/S/RGMII, UAVs, Automotive, Bus Controllers, Defense, LED, Nexus PCIe 

演示

PCIe Colorbar Demo for Lattice Nexus-based FPGAs

PCIe Colorbar Demo displays a series of moving colorbars by streaming the image data using DMA transfers from the FPGA to the host system.

CrossLink-NX, Certus-NX, CertusPro-NX 

SPI, Camera, CSI Camera, Ethernet, PCIe, PMOD, RJ-45, X/S/RGMII, UAVs, Automotive, Bus Controllers, Defense, LED, Nexus PCIe 

演示

PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

The PCI Express DMA Throughput Demo allows to initiate DMA read and write transactions, transferring data from the host to the FPGA and vice versa.

CrossLink-NX, Certus-NX, CertusPro-NX 

SPI, Camera, CSI Camera, Ethernet, PCIe, PMOD, RJ-45, X/S/RGMII, UAVs, Automotive, Bus Controllers, Defense, LED, Nexus PCIe 

演示

基于莱迪思Nexus FPGA的PCIe多功能演示

展示Crosslink-NX FPGA的多功能特性，可访问GPIO、MDIO和I2C寄存器。

CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX 

SPI, Camera, CSI Camera, Ethernet, PCIe, PMOD, RJ-45, X/S/RGMII, UAVs, Automotive, Bus Controllers, Defense, I2C, LED, GPIO, Nexus PCIe 

IP Core

PCI Express for Nexus FPGAs

The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.

CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX 

APB, AHB, AHB-Lite, RTL, PCI, PCIe, Bus Controllers, Defense, Automotive, PCIe Bundle, SDR 

IP Core

PCI Express for Avant and Nexus 2 FPGAs

The Lattice PCIe X8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.

Avant-G, Avant-X, Certus-N2 

AXI, AHB, AHB-Lite, RTL, PCIe, Bus Controllers, Defense, Automotive, Lattice Avant, PCI, PCIe Bundle, SDR, Avionics 

演示

Single Wire Signal Aggregation Demonstration

Single Wire Signal Aggregation Demonstration contains two boards to demonstrate the complete working design in a stand-alone configuration.

iCE40 UltraPlus 

Single Wire, Signal Aggregation, Bus Controllers, GPIO, I2C, I2S, UART, Defense 

Reference Design

单线聚合

使用低成本FPGA以TDM的方式聚合多个数据流，例如I2C、UART、I2S和GPIO，通过单线传输并解聚合。

iCE40 UltraPlus 

Bus Controllers, Signal Aggregation, Single Wire, Defense 

IP Core

​​I3C滤波器IP核

莱迪思I3C滤波器IP从总线上的控制器和从设备的角度来看可以起到隐形中继的作用。

MachXO5-NX 

I3C, Bus Controllers, MIPI Bundle, SMBus, RISC-V 

IP Core

I3C主控IP核

I3C接口在改善总线能耗效率的同时，比I2C速度提高了10倍以上。

CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, iCE40 UltraPlus, Avant-E, Avant-G, Avant-X, Certus-N2, MachXO3D, Mach-NX 

I3C, Bus Controllers, TOR Switch, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense, 5G, Automotive, MIPI Bundle, Lattice Sentry 

IP Core

I3C从设备IP核

莱迪思I3C接口在改善总线能耗效率的同时，比I2C速度提高了10倍以上。

CertusPro-NX, CrossLink-NX, Certus-NX, MachXO5-NX, iCE40 UltraPlus, Avant-E, Avant-G, Avant-X, Certus-N2, MachXO3D, Mach-NX 

I3C, Bus Controllers, TOR Switch, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense, 5G, Automotive, MIPI Bundle 

IP Core

Flash Access IP Core

The Flash Access for MachXO5-NX IP Core enables you to perform write and read access to the internal flash memory of LFMXO5-25 device.

MachXO5-NX 

Bus Controllers, Security, Automotive, Flash, Timer, Memory Controller, Lattice Radiant 

IP Core

MDIO Leader IP Core

MDIO LEADER IP features three different standard interfaces for accessing the control and status signals of Leader: APB, AHB-L and AXI-L.

Avant-E, CertusPro-NX, Certus-N2, Avant-G, Avant-X, Certus-NX, MachXO5-NX 

Bus Controllers, Ethernet, IEEE 802.3, APB, AHB-L, AXI-Lite Interface 

Board

单线聚合演示/开发板

使用全球超小的FPGA以TDM方式聚合多个数据流（例如I2C、I2S和GPIO），通过单线传输和解聚合。

iCE40 UltraPlus 

Single Wire, Bus Controllers, Signal Aggregation 

Reference Design

8N1 UART Transceiver Reference Design

8-bit data, no parity, and 1 stop bit Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel and parallel to serial conversions on data characters received from a peripheral device or CPU

iCE40 UltraPlus, MachXO2  

UART, Bus Controllers, TOR Switch 

演示

I2C主控和从动软核 – 简单读写操作

演示了I2C主控和从动简单的数据读写操作。

iCE40 UltraPlus, MachXO3 

Computing, IoT, TOR Switch, Bus Controllers, I2C 

Reference Design

I2C从动软核

使用Verilog实现软核I2C从动，支持多款莱迪思FPGA系列

CrossLink, CrossLink-NX, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 UltraPlus, LatticeECP3, MachXO2 , MachXO3 

5G, Computing, IoT, TOR Switch, Bus Controllers, I2C 

Reference Design

I2C总线主控软核

使用Verilog实现软核I2C总线主控，支持多款莱迪思FPGA系列

CrossLink, CrossLink-NX, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 UltraPlus, LatticeECP3, MachXO2 , MachXO3, Mach-NX 

5G, Computing, IoT, TOR Switch, Bus Controllers, I2C 

IP Core

GPIO IP核

通用输入/输出（GPIO）外设软IP通过CrossLink-NX的存储器映射接口（LMMI）或高级外设总线接口（APB）控制GPIO

CertusPro-NX, Certus-NX, CrossLink-NX, Mach-NX, iCE40 UltraPlus, MachXO5-NX, Avant-E, Avant-G, Avant-X, Certus-N2 

GPIO Control, APB, Bus Controllers, TOR Switch, Automotive 

IP Core

SPI主控IP核

莱迪思串行外设接口（SPI）主控/从设备IP核是可用于CrossLink-NX的高速同步、串行、全双工接口IP。

CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E, Avant-G, Avant-X, Certus-N2 

SPI, AHB-Lite, APB, Bus Controllers, TOR Switch, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense, Automotive