PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

Allows Direct Memory Acces Read and Write Transactions

The PCIe DMA throughput demo is intended to show the DMA performance between the Nexus FPGA and a host system. At present, the FPGA supported are CrossLink™-NX family and Certus™-NX family. With this application, you can read/write a pattern or counter data between the host system and FPGA memory. There are three pages in the application, GUI Device info, Test Run, and View memory pages.

Hardware Requirements – For CrossLink-NX family, the demo is targeted to the CrossLink-NX PCIe Bridge Board while for the Certus-NX family, the demo is targeted towards the Certus-NX Versa Evaluation Board.This demonstration supports key components for embedded development like DDR3, Ethernet, UART, ADC and SPI Flash.

Transfer size per descriptor – The DMA writes maximum number of descriptors is 255 for a total of 4096*255 bytes of data. For DMA reads, the maximum number of descriptors is 16 for a total of 4096*16 bytes of data.

Direct Memory Access (DMA) operations - The demo performs Direct Memory Access (DMA) operations with the FPGA acting as the bus master. Data is transferred directly to and from the PC memory.

GUI Application - The throughput demo includes a GUI written in Qt, and demonstrates how to open a driver and send control plane read/writes to registers in the IP. The GUI application uses the driver API to communicate with the device hardware. The Driver API is a C++ dynamic library which provides an interface to access the hardware.

Block Diagram


Quick Reference
Nexus Platform PCIe DMA Throughput Demo User Guide
FPGA-UG-02147 1.2 4/12/2022 PDF 3.3 MB
Crosslink-NX PCIe Bridge Board DMA Throughput Demo for Linux
1.0 1/29/2022 ZIP 62.9 MB
Crosslink-NX PCIe Bridge Board DMA Throughput Demo for Windows
1.0 1/29/2022 ZIP 67.2 MB

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