Driver Assistance and ADAS

Reliable, Secure, Low Power ADAS Applications

A higher level of functionalities expected in next-generation cars like driver assistance requires a higher level of performance and multi-sensor fusion systems. Lattice FPGAs address these evolving needs for a flexible and scalable domain controllers design to meet cost and power needs.

  • Enabling parallel sensor data processing with customized low latency networking solution for real time decision making at domain controllers or redundant decision processor systems
  • Enabling low-power multi-sensor interfaces for sensor fusion applications and display interfaces
  • Enabling protection against cyber-attacks while ensuring safety using Lattice FPGA’s hardware-based security, low Soft Error Rates (SER), and Functional Safety (FuSa)
ADAS

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Block Diagram

ADAS and Driver Assistance

Example Use Cases

Real-time data-capture adapter for radar sensing Eval module

  • Supports lab and mobile collection scenarios
  • Captures LVDS data from AWR/ IWR radar sensors
  • Streams output in real-time over low latency 1G Ethernet
  • Controlled via onboard switches or GUI/library

MIPI Splitter for Redundant Processing Systems

  • MIPI speeds supported up to 10 Gbps MIPI D-PHY
  • Support for a variety of sensor interfaces including MIPI, GMII, and PCIe
  • Data pre-processing to reduce SoC loads
  • Low power device for better thermals

Sensor fusion with CrossLink-NX and ECP5

  • Support for heterogeneous sensors with flexible interfaces
  • High-speed interface to SoC including MIPI D-PHY, PCIe, and GMII
  • Accurate and dependable data repackaging from different sensors
  • Single-chip sensor aggregation interfacing with more than dozens of sensors

Sensor aggregation with transmission up to 10m

  • Real-time image and data transfer using Auto SERDES chipsets
  • Sensor aggregation and fast data transfer without skew
  • Longer and cheaper wiring with low EMI
  • Heterogeneous sensor interfaces with FPGAs

Hardware-based SecureBoot and Supply Chain Security

  • NIST compliant Platform Firmware Resiliency (PFR) for ADAS/ DA Domain Controllers
  • Real-time Protect, Detect and Recover for non-bypassable security to cover vulnerable attack points
  • Scalable solution with nanosecond level response for all firmware on the board

Chain of Trust Implementation for Automotive ECUs

  • Hardware Root-of-Trust is the first link in chain of trust that protects entire car system and ECUs
  • Hardened device configuration engine cryptographically authenticates MachXO3D’s configuration image at power-on
  • Embedded security block provides cryptographic functions to authenticate other platform firmware at for the Automotive ECU power-on
  • With instant-on capability MachXO3D is the first device to boot up securely on the platform and as such is an excellent anchor for Chain of Trust

Reference Designs

Lattice Image Signal Processing Reference Design

Reference Design

Lattice Image Signal Processing Reference Design

Configure an ECP5 FPGA-based ISP solution tailored to your Industrial, Medical, and Automotive application.
Lattice Image Signal Processing Reference Design
4 入力 1 出力 MIPI CSI-2 アグリゲーション・リファレンスデザイン

Reference Design

4 入力 1 出力 MIPI CSI-2 アグリゲーション・リファレンスデザイン

ラティス 4 入力 1 出力 MIPI CSI-2 イメージ・アグリゲーション・リファレンスデザイン は 4 つのイメージセンサからのデータを 1 つのデータとして HDMI 経由で出力するデザインを提供
4 入力 1 出力 MIPI CSI-2 アグリゲーション・リファレンスデザイン
MIPI CSI-2 / DSI - OpenLDI I/F ブリッジ・リファレンスデザイン

Reference Design

MIPI CSI-2 / DSI - OpenLDI I/F ブリッジ・リファレンスデザイン

CrossLink ファミリ向けリファレンスデザインは、MIPI DSI 出力のモバイルプロセッサや MIPI CSI-2 出力のイメージセンサと OpenLDI 入力のディスプレイを接続
MIPI CSI-2 / DSI - OpenLDI I/F ブリッジ・リファレンスデザイン
MIPI DSI/CSI-2 to Parallel Bridge Reference Design

Reference Design

MIPI DSI/CSI-2 to Parallel Bridge Reference Design

Modular MIPI/D-PHY Reference Design - Converts MIPI CSI-2 input to Parallel data type output
MIPI DSI/CSI-2 to Parallel Bridge Reference Design

Demos

Lattice Image Signal Processing Demo

Demo

Lattice Image Signal Processing Demo

Provides a complete ISP example design on the Lattice ECP5 FPGA for the Embedded Vision Development Kit, ideal for Industrial, Medical, and Automotive applications.
Lattice Image Signal Processing Demo
DisplayPort 伝送デモ

Demo

DisplayPort 伝送デモ

低消費電力、量産型ECP5向けのDisplayPort 1.4aインターフェース
DisplayPort 伝送デモ
DisplayPort 受信デモ

Demo

DisplayPort 受信デモ

低消費電力で生産価格のECP5用DisplayPort 1.4aインターフェース
DisplayPort 受信デモ
3D Depth Mapping - SGBM Algorithm

Demo

3D Depth Mapping - SGBM Algorithm

Determines the distance between an embedded device and an object using a Semi-Global Block Matching (SGBM) algorithm to determine 64 different disparity levels
3D Depth Mapping - SGBM Algorithm

IP Cores

Helion IONOS画像シグナル処理IPポートフォリオ

IP Core

Helion IONOS画像シグナル処理IPポートフォリオ

Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.
Helion IONOS画像シグナル処理IPポートフォリオ
CSI-2 / DSI D-PHY レシーバ

IP Core

CSI-2 / DSI D-PHY レシーバ

MIPI D-PHY はカメラやディスプレイの標準的なインタフェースです。この IP を使用すると FPGA に D-PHY レシーバを実装できます。
CSI-2 / DSI D-PHY レシーバ
FPD-Link トランスミッタ

IP Core

FPD-Link トランスミッタ

OpenLDI / FPD-Link / LVDS トランスミッタ・インタフェース IP は ピクセルデータフォーマットのビデオデータを FPD-Link やその他の LVDS ディスプレイインタフェースへ変換します。
FPD-Link トランスミッタ
FPD-Link レシーバ

IP Core

FPD-Link レシーバ

OpenLDI / FPD-Link / LVDS レシーバ・インタフェース IP はプロセッサからの OpenLDI / FPD-Link / LVDS 入力をピクセルクロックドメインへ変換します。この IP は他の IP 組み合わせて MIPI DSI ディスプレイインタフェース変換として使用されます。
FPD-Link レシーバ

Automotive Quality & Safety Standard

Support

技術サポート

技術サポートが必要な方はこちら

品質と信頼性

品質と信頼性に関する資料はこちら

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