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  • Lattice mVision MIPI DSI to DisplayPort Demonstration

    Demo

    Lattice mVision MIPI DSI to DisplayPort Demonstration

    The MIPI Display Serial Interface (DSI) to DisplayPort (DP) bridge design features a MIPI D-PHY receiver front-end configuration with four lanes.
    Lattice mVision MIPI DSI to DisplayPort Demonstration
  • ​​Avant MIPI-to-Parallel and Parallel-to-MIPI Bridges Reference Design​

    Reference Design

    ​​Avant MIPI-to-Parallel and Parallel-to-MIPI Bridges Reference Design​

    ​​The design allows quick interface for a processor with a MIPI DSI with an RGB interface, or camera with MIPI CSI-2 to a processor with parallel interface​
    ​​Avant MIPI-to-Parallel and Parallel-to-MIPI Bridges Reference Design​
  • CertusPro-NX N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

    Reference Design

    CertusPro-NX N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

    Modular MIPI/D-PHY Reference Design - Multiple channel image data concatenated horizontally line by line and offers up to eight-channel aggregation.
    CertusPro-NX N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation
  • MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge for CertusPro-NX

    Reference Design

    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge for CertusPro-NX

    Modular MIPI/D-PHY Reference Design - MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge reference design takes DSI or CSI-2 MIPI data and converts them to OpenLDI format on LVDS.
    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge for CertusPro-NX
  • SLVS-EC to MIPI CSI-2 with CertusPro-NX

    Reference Design

    SLVS-EC to MIPI CSI-2 with CertusPro-NX

    Modular MIPI/D-PHY Reference Design - Support advance camera and display interconnections in mobile devices that enable higher performance sensor with optimized power.
    SLVS-EC to MIPI CSI-2 with CertusPro-NX
  • MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Reference Design

    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Modular MIPI/D-PHY Reference Design - Complete solution integrates the Byte to Pixel Converter, CSI-2/DSI D-PHY Receiver and FPD-LINK (OpenLDI) Transmitter
    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge
  • MIPI DSI/CSI-2 to Parallel Bridge Reference Design

    Reference Design

    MIPI DSI/CSI-2 to Parallel Bridge Reference Design

    MIPI to Parallel allows quick interface between a processor and a display using RGB; or between a camera and a processor with a Parallel interface.
    MIPI DSI/CSI-2 to Parallel Bridge Reference Design
  • Parallel to MIPI CSI-2 / DSI Display Interface Bridge Reference Design

    Reference Design

    Parallel to MIPI CSI-2 / DSI Display Interface Bridge Reference Design

    Lattice Parallel to MIPI CSI-2/DSI Display Interface Bridge Reference Design supports low-power (LP) mode during vertical and horizontal blanking.
    Parallel to MIPI CSI-2 / DSI Display Interface Bridge Reference Design
  • Future Electronics Hedgehog Development Board

    Board

    Future Electronics Hedgehog Development Board

    Future Electronics MachXO5-NX breakout board featuring LFMXO5-25-7BBG256C FPGA. Raspberry Pi, Arduino, MikroBus, PMOD, and MIPI camera/display interfaces.
    Future Electronics Hedgehog Development Board
  • MAS LIFCL Evaluation Board

    Board

    MAS LIFCL Evaluation Board

    This modular, flexible and easy-to-use CrossLink-NX 17 board is designed for video applications, including CSI2 MIPI, LVDS HDMI (through PMOD).
    MAS LIFCL Evaluation Board
  • Graphics Acceleration

    Reference Design

    Graphics Acceleration

    Enables a processor to save power in sleep mode while the low-power iCE40 UltraPlus drives a mobile DSI display, and monitors for wake-up signals.
    Graphics Acceleration
  • MIPI DSI Receive Bridge

    Reference Design

    MIPI DSI Receive Bridge

    Allows an AP (Application Processor) or other DSI source to interface to a non-DSI (such as LVDS) display. Up to 4 data lanes at 900 Mbps per lane
    MIPI DSI Receive Bridge
  • iCE40 Ultra Wearable Development Platform

    Board

    iCE40 Ultra Wearable Development Platform

    Peripheral and sensor-rich development platform with iCE 40 Ultra and MachXO2 in a wearable watch form factor.
    iCE40 Ultra Wearable Development Platform
  • 1 Input to 1 Output MIPI DSI Display Interface Bridge

    IP Core

    1 Input to 1 Output MIPI DSI Display Interface Bridge

    Archived IP - Use newer Modular MIPI/D-PHY IP for this function. MIPI DSI to MIPI DSI pass through for updated DCS config, scaling / cropping, or as a redriver.
    1 Input to 1 Output MIPI DSI Display Interface Bridge
  • 1 Input to 2 Output MIPI DSI Display Splitter Bridge

    IP Core

    1 Input to 2 Output MIPI DSI Display Splitter Bridge

    Archived IP - Use newer Modular MIPI/D-PHY IP for this function. Expands the number of display interfaces supported by an Application Processor.
    1 Input to 2 Output MIPI DSI Display Splitter Bridge
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