Parallel to MIPI CSI-2 / DSI Display Interface Bridge Reference Design

Bridging Traditional Processors with Mobile Display Interfaces

MIPI D-PHY is a practical PHY for typical camera and display applications. It is designed to replace traditional parallel bus based on LVCMOS or LVDS. However, many processors and displays/cameras still use RGB, CMOS, or MIPI Display Pixel Interface (DPI) as interface.

The Parallel to MIPI reference design allows the quick interface for a processor with an RGB interface to a display with a MIPI DSI interface or a camera with a CMOS interface to a processor with CSI-2 interface. The Lattice Semiconductor Parallel to MIPI D-PHY Interface reference design provides this conversion for Lattice Semiconductor CrossLink™-NX devices. This is useful for wearable, tablet, human machine interfacing, medical equipment and many other applications.


  • Compliant with MIPI D-PHY v1.2, MIPI DSI v1.2, and MIPI CSI-2 v1.2 Specifications
  • Supports MIPI DSI and MIPI CSI-2 interfacing up to 6 Gb/s for Soft D-PHY and up to 10 Gb/s for Hard D-PHY
  • Supports 1, 2, or 4 MIPI D-PHY data lanes
  • Supports non-burst mode with sync events for transmission of DSI packets only
  • Supports low-power (LP) mode during vertical and horizontal blanking
  • Supports common MIPI DSI compatible video formats (RGB888, RGB666)

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Block Diagram

Parallel To CSI-2/DSI bridge Reference Design

CrossLink and CrossLink-NX Modular IP Support Table


Technical Resources
Select All
Parallel to MIPI with CertusPro-NX - Source Code
FPGA-RD-02239 1.0 9/17/2021 ZIP 35.2 MB
Parallel to MIPI with CertusPro-NX - Documentation
FPGA-RD-02239 1.0 9/17/2021 PDF 1.2 MB
Parallel to MIPI with CrossLink-NX - Source Code
FPGA-RD-02214 1.0 3/2/2021 ZIP 12 MB
Parallel to MIPI with CrossLink-NX - Documentation
FPGA-RD-02214 1.0 3/2/2021 PDF 1.5 MB

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