Parallel to MIPI CSI-2 / DSI Display Interface Bridge Reference Design

Bridging Traditional Processors with Mobile Display Interfaces

​​The Mobile Industry Processor Interface (MIPI®) D-PHY was developed primarily to support camera and display interconnections in mobile devices, and MIPI D-PHY has become the primary high-speed PHY solution in industry for these applications in smartphones. MIPI D-PHY is typically used in conjunction with MIPI Camera Serial Interface-2 (CSI-2) and MIPI Display Serial Interface (DSI) protocol specifications. The interface meets the demanding requirements of low power, low noise generation, and high noise immunity that mobile phone designs demand. MIPI D-PHY is a practical PHY for typical camera and display applications which is designed to replace traditional parallel bus based on LVCMOS or LVDS. However, many processors and displays and cameras still use RGB, CMOS, or MIPI Display Pixel Interface (DPI) as interface.

​The Lattice Semiconductor Parallel-to-MIPI reference design allows the quick interface for a processor with an RGB interface to a display with a MIPI DSI interface, or a camera with a CMOS interface to a processor with CSI-2 interface. This reference design provides the conversion for CertusPro-NX, CrossLink-NX, and CrossLink™ devices and is useful for wearable, tablet, human machine interfacing, medical equipment, and many other applications.

Features

  • Supports 1, 2, or 4 MIPI D-PHY data lanes
  • Supports low power (LP) mode during vertical and horizontal blanking
  • MIPI CSI-2/DSI and D-PHY support:
    • Supports MIPI DSI and MIPI CSI-2 interfacing up to 6 Gb/s for Soft D-PHY and up to 10 Gb/s for Hard D-PHY applicable only for CrossLink-NX devices
    • Supports MIPI D-PHY interface from 80 Mb/s up to 1.5 Gb/s (Hardened D-PHY / Gear 16) applicable only for CrossLink/CrossLinkPlus devices.
  • Compliance Specification:
    • MIPI D-PHY v1.1, MIPI DSI v1.1, and MIPI CSI-2 v1.1 for CrossLink devices
    • MIPI D-PHY v1.2, MIPI DSI v1.2, and MIPI CSI-2 v1.2 for CertusPro-NX and CrossLink-NX devices
  • Compatible Video Formats:
    • Supports common MIPI DSI compatible video formats (RGB888, RGB666) for CertusPro-NX, CrossLink-NX, and CrossLink™ devices
    • Supports common MIPI CSI-2 compatible video formats (RGB888, RAW8, RAW10, RAW12) CertusPro-NX and CrossLink-NX, and CrossLink™ devices and (RAW14) supported only for CrossLink-NX devices

Jump to

Block Diagram

Parallel to MIPI CSI-2 / DSI Display Interface Bridge Reference Design Block Diagram for CertusPro-NX​

Parallel to MIPI CSI-2 / DSI Display Interface Bridge Reference Design Block Diagram for CrossLink-NX​

Parallel to MIPI CSI-2 / DSI Display Interface Bridge Reference Design Block Diagram for CrossLink​

CrossLink and CrossLink-NX Modular IP Support Table

Resource Utilization

Configurations Targeting LFCPNX
Configuration LUT
(Utilization/Total)
FF
(Utilization/Total)
EBR
(Utilization/Total)
I/O
(Utilization/Total)
4-lane, Gear 8, Soft D-PHY, CSI-2, RAW14, 1 Pixels/clock 763/79872 602/80769 1/208 25/299
4-lane, Gear 8, Soft D-PHY, CSI-2, RAW12, 6 Pixels/clock 1109/79872 754/80769 4/208 88/299
4-lane, Gear 8, Soft D-PHY, DSI, RGB888, 2 Pixels/clock 803/79872 857/80769 3/208 64/299
4-lane, Gear 8, Soft D-PHY, DSI, RGB666, 2 Pixels/clock 929/79872 829/80769 2/208 52/299
Configurations Targeting LIFCL
Configuration LUT
(Utilization/Total)
FF
(Utilization/Total)
EBR
(Utilization/Total)
I/O
(Utilization/Total)
4-lane, Gear 16, Hard D-PHY, DSI, RGB888, 4 Pixels/clock 19 4 6 102
1-lane, Gear 8, Soft D-PHY, DSI, RGB888, 1 Pixels/clock 4 2 1 34
4-lane, Gear 16, Hard D-PHY, CSI-2, RAW12, 10 Pixels/clock 5 3 8 126
1-lane, Gear 8, Hard D-PHY, CSI-2, RAW8, 1 Pixels/clock 2 1 1 13

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
CertusPro-NX Parallel to MIPI CSI-2/DSI Display Interface Bridge Reference Design - Source Code
7/4/2023 ZIP 35.2 MB
CertusPro-NX Parallel to MIPI CSI-2/DSI Display Interface Bridge Reference Design - User Guide
FPGA-RD-02239 1.2 12/19/2023 PDF 1.5 MB
CrossLink-NX Parallel to MIPI CSI-2/DSI Display Interface Bridge Reference Design - Source Code
5/20/2024 ZIP 2.4 MB
CrossLink-NX Parallel to MIPI CSI-2/DSI Display Interface Bridge Reference Design - User Guide
FPGA-RD-02214 1.2 5/20/2024 PDF 1.4 MB
CrossLink Parallel to MIPI CSI-2/DSI Display Interface Bridge Reference Design - Source Code
8/30/2024 ZIP 1.2 MB
CrossLink Parallel to MIPI CSI-2/DSI Display Interface Bridge Reference Design - User Guide
FPGA-RD-02293 1.0 8/30/2024 PDF 1 MB

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