Byte to Pixel Converter IP Core

Convert Parallel Data From a D-PHY Receiver into Pixel Format

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Related Applications

Lattice Semiconductor Byte-to-Pixel Converter IP converts CSI-2/DSI standard-based video payload packets from D-PHY Receiver Module output to pixel format. In addition, Byte-to-Pixel Converter IP generates camera and video control signals in the pixel domain based on CSI-2 or DSI synchronization packets.

Resource Utilization details are available in the IP Core User Guide.

Features

  • MIPI DSI compatible video formats
  • MIPI CSI-2 compatible video formats
  • 1-, 2-, or 4-lane inputs
  • 8-bit (gear 8) or 16-bit (gear 16) inputs per lane
  • 1, 2, or 4 output pixels per pixel clock cycle

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Block Diagram

Byte to Pixel Converter Block DiagramExpand Image

Resource Utilization

IP Configuration for Avant Family
LAV-AT-500E-3LFG1156C
Device LUTs Registers sysMem EBRs Programmable I/O
CSI2,RAW10,Byte Side Clock
Frequency 100 MHz, Pixel Side
Clock Frequency 80 MHz, Word Count 720		 545 304 1 19
CSI2,RGB888,Byte Side Clock
Frequency 150 MHz, Pixel Side
Clock Frequency 100 MHz, Word Count 720		 589 351 1 19
CSI2,RGB888, Number of RX
Lanes 4, Byte Side Clock
Frequency 50 MHz, Pixel Side
Clock Frequency 160 MHz, Word Count 2052 		670 433 1 19
CSI2,RGB888, Number of RX
Lanes 4, Byte Side Clock
Frequency 112.5 MHz, Pixel Side
Clock Frequency 150 MHz, Word Count 3600		 616 406 1 19
DSI,RGB666, Number of RX
Lanes 1, Byte Side Clock
Frequency 108 MHz, Pixel Side
Clock Frequency 96 MHz, Word Count 2160		 587 392 1 22
DSI,RGB666, Number of RX
Lanes 2, Byte Side Clock
Frequency 140.625 MHz, Pixel
Side Clock Frequency 125 MHz, Word Count 2160		 631 371 1 22

Note: The distributed RAM utilization is accounted for in the total LUT4 utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.

IP Configuration for Nexus Family
Device LUTs Registers sysMem EBRs Programmable I/O
CSI2,RAW10,Byte Side Clock
Frequency 100 MHz, Pixel Side
Clock Frequency 80 MHz, Word Count 720		 369 287 1 51
CSI2,RGB888,Byte Side Clock
Frequency 150 MHz, Pixel Side
Clock Frequency 100 MHz, Word Count 720		 399 324 1 73
CSI2,RGB888, Number of RX
Lanes 4, Byte Side Clock
Frequency 50 MHz, Pixel Side
Clock Frequency 160 MHz, Word Count 2050 		495 363 2 75
CSI2,RGB888, Number of RX
Lanes 4, Byte Side Clock
Frequency 112.5 MHz, Pixel Side
Clock Frequency 150 MHz, Word Count 3600		 421 386 2 89
DSI,RGB666, Number of RX
Lanes 1, Byte Side Clock
Frequency 108 MHz, Pixel Side
Clock Frequency 96 MHz, Word Count 2160		 534 337 1 68
DSI,RGB666, Number of RX
Lanes 2, Byte Side Clock
Frequency 140.625 MHz, Pixel
Side Clock Frequency 125 MHz,
Number of Output Pixels 2,
Word Count 21600		 649 427 1 102

Note: The distributed RAM utilization is accounted for in the total LUT4 utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.

IP Configuration for CrossLink Family
IP User-Configurable Parameters Slices LUTs Registers sysMem EBRs Programmable I/O
RGB888,
Gear 16,
4-lane,
2 pixel output		 463 511 548 6 0
RGB888,
Gear 8,
4-lane,
2 pixel output		 267 289 333 3 0
RGB888,
Gear 16,
2-lane,
1 pixel output		 249 259 305 3 0
RGB888,
Gear 8,
2-lane,
1 pixel output		 215 238 264 2 0

Ordering Information

The Byte to Pixel core is available for FREE for use in Diamond design software.

For Radiant design software, the Byte to Pixel core must be purchased:

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
Certus-N2 BYTE-PIXEL-CN2-UT BYTE-PIXEL-CN2-US
Avant-G BYTE-PIXEL-AVG-UT BYTE-PIXEL-AVG-US
Avant-X BYTE-PIXEL-AVX-UT BYTE-PIXEL-AVX-US
Avant-E BYTE-PIXEL-AVE-UT BYTE-PIXEL-AVE-US
CrossLink-NX BYTE-PIXEL-CNX-UT BYTE-PIXEL-CNX-US
Certus-NX BYTE-PIXEL-CTNX-UT BYTE-PIXEL-CTNX-US
CertusPro-NX BYTE-PIXEL-CPNX-UT BYTE-PIXEL-CPNX-US
MachXO5-NX BYTE-PIXEL-XO5-UT BYTE-PIXEL-XO5-US
Bundled  MIPI-BNDL-UT MIPI-BNDL-US

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the Byte-to-Pixel IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Byte-to-Pixel Converter IP - Lattice Diamond Software
FPGA-IPUG-02027 1.4 10/14/2021 PDF 1.7 MB
Byte-to-Pixel Converter IP Core - User Guide
FPGA-IPUG-02079 2.0 2/25/2025 PDF 1.8 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Byte-to-Pixel Converter IP Core - Release Notes
FPGA-RN-02019 1.0 2/25/2025 PDF 221.1 KB

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