Pixel to Byte Converter IP Core

Convert Pixel Format Data to Parallel Byte Format

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The increasing demand for better displays makes bridging applications very popular. Mobile Industry Processor Interface (MIPI®) D-PHY has become the industry’s primary high-speed PHY solution for camera and display interconnection in mobile devices. It is typically used in conjunction with MIPI Camera Serial Interface-2 (CSI-2) and MIPI Display Serial Interface (DSI) protocol specifications. It meets the requirements of low-power, low noise generation, and high noise immunity that mobile phone designs demand.

MIPI D-PHY is designed to replace traditional parallel bus based on LVCMOS or LVDS. However, many processors and displays/cameras still use an RGB or CMOS as interface. So, to connect to a MIPI D-PHY IP, a converter logic is required to convert the parallel interface into MIPI D-DPHY byte packet compatible format.

Features

  • Support for RGB888, RGB666, RAW8, RAW10, RAW12, RAW14, RAW16, YUV420/YUV422 8/10-bit video formats
  • Conversion of 1, 2, 4, 6, 8, or 10 pixels per pixel clock into MIPI D-DPHY byte packet compatible format
  • Support for byte arrangement for 1, 2, or 4 MIPI D-PHY data lanes
  • Optional AXI4 Streaming interface for byte and pixel data
  • APB interface for configuration and status

Block Diagram

Byte to Pixel Converter Block DiagramExpand Image

Performace and Size

Resource Utilization
Device LUTs Registers sysMEM EBRs Programmable I/O
Default 455 259 1 4
DSI, RGB666, Number of TX Lanes 2 553 296 1 12
CSI-2, RGB888, Number of TX Lanes 4 503 372 1 28
CSI-2, RAW8, Number of TX Lanes 4 394 319 1 28
DSI, RGB888, Number of TX Lanes 4, Number of Input Pixel Per Clock 4, TX Gear 16 689 562 2 60
CSI-2, RGB888, Number of TX Lanes 2, TX Gear 16 503 372 1 28
CSI-2, RAW10, Number of TX Lanes 2, Number of Input Pixel Per Clock 2 471 281 1 12
CSI-2, RAW14, Numbber of TX Lanes 4, Number of Input Pixel Per Clock 2, TX Gear 16 913 696 2 60

Note: The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distributed among logic, distributed RAM, and ripple logic.

Ordering Information

The Pixel to Byte core is available for FREE for use in Diamond design software.

For Radiant design software, the Pixel to Byte core must be purchased:

  Part Number
Device Family Single Design Multi-Site Subscription
Avant-E PIXEL-BYTE-AVE-U PIXEL-BYTE-AVE-UT PIXEL-BYTE-AVE-US
MachXO5-NX PIXEL-BYTE-XO5-U PIXEL-BYTE-XO5-UT PIXEL-BYTE-XO5-US
CertusPro-NX PIXEL-BYTE-CPNX-U PIXEL-BYTE-CPNX-UT PIXEL-BYTE-CPNX-US
Certus-NX PIXEL-BYTE-CTNX-U PIXEL-BYTE-CTNX-UT PIXEL-BYTE-CTNX-US
CrossLink-NX PIXEL-BYTE-CNX-U PIXEL-BYTE-CNX-UT PIXEL-BYTE-CNX-US

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the Pixel-to-Byte IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Pixel-to-Byte Converter IP - Lattice Diamond Software
FPGA-IPUG-02026 1.3 3/20/2020 PDF 2.1 MB
Pixel to Byte Converter IP Core - Lattice Radiant Software
FPGA-IPUG-02094 1.5 2/7/2023 PDF 1.5 MB

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