Datacenter Switches

NIST compliant, Secure, Scalable - Control, Power and Thermal management PLD

Modern-day switches are required to implement security in hardware to ensure end-to-end security to combat the presence of malicious actors in the supply chain. To meet the ever increasing demand on data throughput, the main switch and control processor are becoming more complex and with increased TDP. This makes the power management and thermal management a lot more complex. With the increased number of communication ports, the control PLD is expected to control many I2C channels, LEDs and sense more signals.

  • Standardized, scalable control PLD family with wide range of density and I/O options
  • Lattice’s PFR Stack enables integration of Platform Firmware Resilience (PFR) function to the Control PLD
  • Integrates power and thermal management functions

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Block Diagram

Switches

Example Use Cases

Control PLD in the CPU

  • Control PLD for sequencing and side-channel logic, SGPIO
  • Secure Platform RoT for Platform Firmware Resilience (CPU)
    • Supply Chain Protection
    • RTS- Encryption Key Storage, data sealing (network usage logs)

Control PLD in Switch Fabric

  • Control PLD + PM for sequencing, glue logic
  • Control interface for multi-port card
  • Secure Platform RoT
    • PFR - Switch SoC, BMC and CPU Firmware(ComExp)
    • Onboarding of multi-port card

CPLD in Multi-port

  • Control PLD + PM for sequencing, glue logic
  • Control Interface for multi-port card
  • Secure Platform RoT
    • PFR - Switch SoC, BMC and CPU Firmware(ComExp)
    • Onboarding of multi-port card

Overall Power & Thermal Management

  • Precision power monitoring with telemetry support
  • Accurate temperature monitoring
  • Fan control
  • Power supply trimming and margining
  • Fault log with time stamp

Reference Designs

8N1 UART Transceiver Reference Design

Reference Design

8N1 UART Transceiver Reference Design

8-bit data, no parity, and 1 stop bit Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel and parallel to serial conversions on data characters received from a peripheral device or CPU
8N1 UART Transceiver Reference Design
Soft I2C Bus Master

Reference Design

Soft I2C Bus Master

Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families
Soft I2C Bus Master
Soft I2C Slave Peripheral

Reference Design

Soft I2C Slave Peripheral

Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families
Soft I2C Slave Peripheral
I2C Bus Master

Reference Design

I2C Bus Master

Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
I2C Bus Master

Demo

Soft I2C Master and Slave – Simple Write and Read

Demo

Soft I2C Master and Slave – Simple Write and Read

Demonstrates the operation of an I2C Master and Slave doing simple write and read of data.
Soft I2C Master and Slave – Simple Write and Read
Power Sequencing with Fault Logging Demo

Demo

Power Sequencing with Fault Logging Demo

Uses L-ASC10 to monitor, sequence four separate Power Planes from a central control point. Logs faults with timestamps. Expandable.
Power Sequencing with Fault Logging Demo

IP Cores

RISC-V MC CPU IP Core

IP Core

RISC-V MC CPU IP Core

Propel IP Module: 32-bit RISC-V processor core with optional Timer and PIC sub-modules, connects via AHB-Lite bus to other Propel IP modules and more.
RISC-V MC CPU IP Core
I3C Master IP Core

IP Core

I3C Master IP Core

Bus controller following the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
I3C Master IP Core
I3C Slave IP Core

IP Core

I3C Slave IP Core

Interfaces to the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
I3C Slave IP Core
AHB-Lite Interconnect Module

IP Core

AHB-Lite Interconnect Module

Propel IP Module: Fully parameterized interconnect for AHB-Lite systems - bus widths of 8 to 1024 bits, address widths up to 32 bits, 32 masters and 32 slaves.
AHB-Lite Interconnect Module
AHB-Lite to APB Bridge Module

IP Core

AHB-Lite to APB Bridge Module

Propel IP Module: Bridges high-speed AHB-lite to low-power APB. Data bus widths up to 32 bits. Address width up to 32 bits.
AHB-Lite to APB Bridge Module

Development Kits & Boards

ECP5 Evaluation Board

Board

ECP5 Evaluation Board

Evaluation and development for ECP5-5G FPGA - 85K LUTs. Includes generous IO access and easy expansion to PMOD, Arduino, RaspberryPI, SERDES interface and more
ECP5 Evaluation Board
MachXO3D Breakout Board

Board

MachXO3D Breakout Board

Small low-cost board with generous access to MachXO3D FPGA IO for general purpose evaluation and development
MachXO3D Breakout Board
MachXO3D Development Board

Board

MachXO3D Development Board

General purpose evaluation and development for MachXO3D with generous IO access and multiple expansion connectors RaspberryPi, Arduino, Lattice Versa, and more.
MachXO3D Development Board
ECP5 Versa Development Kit

Board

ECP5 Versa Development Kit

Evaluate and develop for key connectivity features of the ECP5 FPGA, including PCI Express, Gigabit Ethernet, DDR3 and generic SERDES, includes numerous demos.
ECP5 Versa Development Kit
MachXO2 Breakout Board

Board

MachXO2 Breakout Board

A simple low-cost board that provides complete I/O access to the MachXO2 plus LEDs, Prototyping Area Power and Programming on-board.
MachXO2 Breakout Board

Support

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Quality & Reliability

Reference Material to Help Answer Your Questions

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