Soft I2C Bus Master

Efficient and flexible I2C design supporting many Lattice FPGA families

I2C supporting popular Lattice FPGA families The I2C, or Inter-Integrated Circuit, is a two-wire interface capable of half-duplex serial communication at moderate to high speeds of up to a few megabits per second. The I2C incorporates an addressing system to identify the multiple I2C slaves on the I2C bus. The system utilizes two bidirectional lines, which are the SDA (Serial Data) and SCL (Serial Clock).

Includes source code compliant to I2C Specification This reference design implements an I2C Master Module on any Lattice FPGA using Lattice Diamond® 3.11 and Lattice Radiant® 2.1. It follows the I2C specification to provide device addressing, read/write operation, and an acknowledgement mechanism. It adds an instant I2C compatible interface to any component in the system.

Configure to match your system’s needs. The programmable nature of FPGA devices provides you with the flexibility of configuring the I2C master device to any legal slave address. This avoids the potential slave address collision on an I2C bus with multiple slave devices.


  • Supports a wide array of Lattice FPGAs such as MachXO2™, MachXO3™, LatticeECP3™, ECP5™, CrossLink™, CrossLink™-NX, and iCE40 UltraPlus™
  • Supports 7-bit and 10-bit slave addressing
  • Supports operation at 100 kHz (Standard Mode) and 400 kHz (Fast Mode)
  • Supports repeated start operations
  • Interrupt generation logic and Byte-wide clock stretching

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Block Diagram

Soft I2C Bus Master Block Diagram

Performance and Size

Device Family Language Utilization fMAX (MHz) I/O
LatticeECP3 Verilog 290 >32 Up to 69 ports
ECP5 Verilog 289 >32 Up to 69 ports
CrossLink Verilog ~263 >32 Up to 69 ports
CrossLink-NX Verilog 290 >32 Up to 69 ports
iCE40 UltraPlus Verilog 282 >32 Up to 69 ports
MachXO2 Verilog 292 >32 Up to 69 ports
MachXO3 Verilog 292 >32 Up to 69 ports

Note: The performance and design sizes shown above are estimates based on sample implementations. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the Reference Design documentation for details.


Technical Resources
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Generic Soft I2C Master Controller - Documentation
FPGA-RD-02201 1.0 12/10/2020 PDF 1.2 MB
Generic Soft I2C Master Controller - Project Files
FPGA-RD-02201 1.0 12/10/2020 ZIP 1.2 MB

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