Soft I2C Slave Peripheral

Efficient and flexible I2C design supporting many Lattice FPGA families

I2C supporting popular Lattice FPGA families The I2C, or Inter-Integrated Circuit, is a two-wire interface capable of half-duplex serial communication at moderate to high speeds of up to a few megabits per second. The I2C incorporates an addressing system to identify the multiple I2C slaves on the I2C bus. The system utilizes two bidirectional lines, which are the SDA (Serial Data) and SCL (Serial Clock).

Includes source code compliant to I2C Specification This reference design implements an I2C slave module on any Lattice FPGA using Lattice Diamond® 3.11 and Lattice Radiant® software 2.1. It follows the I2C specification to provide device addressing, read/write operation and an acknowledgement mechanism.

Configure to match your system’s needs. The programmable nature of FPGA devices provides you with the flexibility of configuring the I2C slave device to any legal slave address. This avoids the potential slave address collision on an I2C bus with multiple slave devices.


  • Supports a wide array of Lattice FPGAs such as MachXO2™, MachXO3™, LatticeECP3™, ECP5™, CrossLink™, CrossLink™-NX, and iCE40 UltraPlus™
  • Supports 7-bit and 10-bit slave addressing, with a software-programmable slave address
  • Supports clock stretching
  • Supports repeated start condition
  • Supports I2C SCL range of up to 1 MHz with the following I2C speed modes tested:
    • Standard Mode – 100 kHz
    • Fast Mode – 400 kHz
    • Fast Mode Plus – 1 MHz

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Block Diagram

Soft I2C Slave Peripheral Block Diagram

Performance and Size

Device Family Language Utilization fMAX (MHz) I/O
LatticeECP3 Verilog 149 >32 25
ECP5 Verilog 149 >32 25
CrossLink Verilog ~149 >32 25
CrossLink-NX Verilog 157 >32 25
iCE40 UltraPlus Verilog 136 >32 25
MachXO2 Verilog 148 >32 25
MachXO3 Verilog 148 >32 25

Note: The performance and design sizes shown above are estimates based on sample implementations. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the Reference Design documentation for details.


Technical Resources
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Generic Soft I2C Slave Peripheral - Documentation
FPGA-RD-02193 1.3 8/10/2023 PDF 584.3 KB
Generic Soft I2C Slave Peripheral - Project Files
12/27/2023 ZIP 51.9 KB

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