Unmanned Aerial Vehicles (UAVs)

Low power innovations for the next frontier of aviation

Related Applications

During the last 25 years, defense-grade unmanned aerial vehicles have benefitted from Lattice's advances in vision processing and sensor fusion to solve complex national security challenges. In the coming years, advances in process technology, algorithms and machine learning will deliver a new set of robust capabilities and use cases while advancing flight control and autonomy, lowering mission costs and extending the payload and duration of missions.

Focused on vision processing performance at the lowest power and always-on AI built on highly reliable FD-SOI platform, Lattice delivers industry leading solutions to help develop next generation avionics with reduced risk and time to market.

Key Lattice FPGA Features & Benefits

  • Best-in-class performance for vision processing and video bridging applications with up to 75% lower power vs similar FPGAs
  • Small form factor packaging with sizes as small as 4 mm x 4 mm
  • Built-in high-speed connectivity including embedded MIPI DPHY, PCIE, DDR3, 1.5 Gbps LVDS and integrated Analog-to-Digital converters simplify data acquisition and processing, sensor fusion, RF front-end interfaces, and control plane implementations
  • Lowest power, parallel multi-sensor interfaces for sensor fusion and low latency networking solutions help integrate real time data to provide a single, autonomous operating picture and enable more informed decisions

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Example Applications

Image Sensor Processing

  • Bridge one or multiple CSI-2 image sensors to processor interface (PCIe, CMOS, CSI-2)
  • Integrate full functional universal video pipeline
  • Examples: Debayer, color correction matrix, RGB gain, gamma correction…
  • Offloads ISP functionality from the processor

Sensor Aggregation

  • Aggregate up to 11 MIPI CSI-2 image sensors into one MIPI CSI-2 output
  • Stitch data together into larger horizontal video frame
  • Use external DDR memory to stitch data into larger vertical video frame
  • Arbitrate data from image sensors using unique virtual channel numbers
  • Extend limited processor sensor interface capability and connect more sensors

Co-processing

  • Off-load CPU by using Certus-NX as a co-processor to accelerate complex functions
  • DDR3 & LPDDR2 interface support (up to 1066 Mbps) and on-chip embedded memory (up to 2.9 Mbit) provide multiple options for data buffering
  • Compact packages as small as 6x6 mm with PCIe and DDR memory interface support

Reference Designs

Human Face Identification

Reference Design

Human Face Identification

Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.
Human Face Identification
PDM Microphone Aggregation

Reference Design

PDM Microphone Aggregation

Aggregate up to 8 PDM microphones and connection to a processor over I2S or SPI with no impact in audio quality. Ideal for beam-forming. PCM output at 48HKz.
PDM Microphone Aggregation
Infrared Remote Tx/Rx Reference Designs

Reference Design

Infrared Remote Tx/Rx Reference Designs

Implements an interface to IR receive and/or IR transmit. This includes PWM (pulse width modulation) timing and protocol conversion to an SPI /I2C bus
Infrared Remote Tx/Rx Reference Designs
LED/OLED Driver

Reference Design

LED/OLED Driver

Drive an LED via WISHBONE bus. Default is targeted to a GM1WA55311A LED but can be used to control other LEDs or OLEDs with similar functions.
LED/OLED Driver

IP Cores

CNN Compact Accelerator IP

IP Core

CNN Compact Accelerator IP

Implement AI solutions with CNNs or BNNs that have power consumption in the mW range. Works with Lattice Neural Network Compiler software tool.
CNN Compact Accelerator IP
CNN Plus Accelerator IP

IP Core

CNN Plus Accelerator IP

Implement Ultra-Low Power AI solutions with CNNs. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
CNN Plus Accelerator IP
Color Space Converter (CSC)

IP Core

Color Space Converter (CSC)

Free IP core - supports color space conversion and related CODEC functions from 8-16 bits wide, precision up to 18 bits. RGB YCbCr CMYK and more.
Color Space Converter (CSC)
Gamma Corrector

IP Core

Gamma Corrector

A highly-parameterizable, multi-color plane gamma correction system. It can support almost any custom gamma correction requirement
Gamma Corrector
2D Scaler

IP Core

2D Scaler

Highly-configurable design to convert input video frames of one size to output video frames of a different size
2D Scaler

Development Kits & Boards

Embedded Vision Development Kit

Board

Embedded Vision Development Kit

Three-board Video Interface Platform (VIP) modular kit. Includes 2 MIPI/D-PHY camera input, FPGA processing, HDMI output. More Input/Output boards available.
Embedded Vision Development Kit
Lattice Sentry Demo Board for MachXO3D

Board

Lattice Sentry Demo Board for MachXO3D

A complete platform to help you develop and test a NIST 800-193-compliant PFR solution. Includes numerous features to enable debug, interface and expansion
Lattice Sentry Demo Board for MachXO3D
Certus-NX Versa Evaluation Board

Board

Certus-NX Versa Evaluation Board

Contains a rich set of high-performance interfaces for development with the Certus-NX FPGA, including PCIe, DDR3, Ethernet PHY, cameras, PMOD and more.
Certus-NX Versa Evaluation Board
HM01B0 UPduino Shield

Board

HM01B0 UPduino Shield

A complete development kit for implementing Artificial Intelligence (AI) using vision and sound as sensory inputs to a low-cost, low-power iCE40 UltraPlus FPGA.
HM01B0 UPduino Shield
HDMI VIP Input Board

Board

HDMI VIP Input Board

Dual HDMI input for Video Interface Platform (VIP)
HDMI VIP Input Board

Demos

Human Presence Detection

Demo

Human Presence Detection

Uses an artificial intelligence (AI) algorithm to detect human presence with either the powerful ECP5 FPGA, or small, low-power iCE40 UltraPlus FPGA.
Human Presence Detection
Speed Sign Detection

Demo

Speed Sign Detection

Uses a Convolutional Neural Network in the ECP5 FPGA to detect speed limit signs and determine the indicated speed.
Speed Sign Detection

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Soft Error Detection (SED)/Correction (SEC) Usage Guide for Nexus Platform
FPGA-TN-02076 1.1 6/24/2020 PDF 1005.1 KB
Multi-Boot Usage Guide for Nexus Platform
FPGA-TN-02145 1.1 5/31/2020 PDF 1.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Soft Error Detection (SED)/Correction (SEC) Usage Guide for Nexus Platform
FPGA-TN-02076 1.1 6/24/2020 PDF 1005.1 KB
Multi-Boot Usage Guide for Nexus Platform
FPGA-TN-02145 1.1 5/31/2020 PDF 1.2 MB

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