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  • ​​JESD204B IP Core​

    IP Core

    ​​JESD204B IP Core​

    ​​The Lattice JESD204B IP Core is a high-speed serial interface used between data converters, and the FPGA device to replace traditional interfaces.​
    ​​JESD204B IP Core​
  • CertusPro-NX Voice and Vision Machine Learning Board

    Board

    CertusPro-NX Voice and Vision Machine Learning Board

    Design AI use cases for the Edge quickly! This board along with the Lattice sensAI solution stack provide the tools for developing vision and audio-based AI applications.
    CertusPro-NX Voice and Vision Machine Learning Board
  • Video Scaler IP Core

    IP Core

    Video Scaler IP Core

    The Lattice Video Scaler IP Core is used to scale up or scale down the resolution of a video stream.
    Video Scaler IP Core
  • eUSB 3.1 FMC

    Board

    eUSB 3.1 FMC

    eUSB 3.1 FMC board is to validate USB 3.1 functionality with FPGA’s inbuilt serial transceivers. It has ULPI PHY chip to validate USB 2.0 functionality.
    eUSB 3.1 FMC
  • 5G O-RU L-PHY & H-PHY IP Cores

    IP Core

    5G O-RU L-PHY & H-PHY IP Cores

    ​​Yongatek's L-PHY IP in Lattice CertusPro-NX FPGA: 3GPP TS38.212 Release 16 compatible, O-RAN Alliance compliant, up to 6GHz, ideal for mid-power RF apps.​
    5G O-RU L-PHY & H-PHY IP Cores
  • FFT Compiler IP Core

    IP Core

    FFT Compiler IP Core

    The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.
    FFT Compiler IP Core
  • FIR Filter Generator IP Core

    IP Core

    FIR Filter Generator IP Core

    This IP core is a widely configurable, multi-channel FIR filter, implemented using high performance sysDSP™ blocks available in Lattice devices.
    FIR Filter Generator IP Core
  • Coordinate Rotational Digital Computer (CORDIC) IP Core

    IP Core

    Coordinate Rotational Digital Computer (CORDIC) IP Core

    The Lattice CORDIC IP uses full internal precision while allowing variable output precision with several choices for rounding.
    Coordinate Rotational Digital Computer (CORDIC) IP Core
  • 2D Scaler IP Core

    IP Core

    2D Scaler IP Core

    Highly-configurable design to convert input video frames of one size to output video frames of a different size
    2D Scaler IP Core
  • Numerically Controlled Oscillator

    IP Core

    Numerically Controlled Oscillator

    Also called a Direct Digital Synthesizer (DDS). Supports multiple channels and a Quadrature Amplitude Modulation (QAM) mode, plus other usual configurations
    DSP 
    Numerically Controlled Oscillator
  • 2D FIR Filter

    IP Core

    2D FIR Filter

    Performs real-time 2D convolution of windowed portions of incoming video frames with coefficient matrices held in internal memory
    2D FIR Filter
  • Median Filter

    IP Core

    Median Filter

    Popular method of noise removal in signal processing. Supports many video frame sizes.
    Median Filter
  • 8-bit Correlator

    IP Core

    8-bit Correlator

    Correlates an incoming data stream to a stored binary pattern called a code / coefficient sequence. Configure to 8 bit width, 256 channels, 2048 taps and more.
    8-bit Correlator
  • Interleaver/De-Interleaver

    IP Core

    Interleaver/De-Interleaver

    Supports rectangular block type and convolutional architectures. Rectangular interleaving arranges the input data row-wise in a matrix
    DSP 
    Interleaver/De-Interleaver
  • JESD207 IP

    IP Core

    JESD207 IP

    Implements baseband (BB) side data and control plane paths to connect to a radio front-end (RF) transceiver device with integrated ADC and DAC.
    JESD207 IP
  • Distributed Arithmetic FIR Filter Generator

    IP Core

    Distributed Arithmetic FIR Filter Generator

    Implements a highly configurable, multi-channel DA-FIR filter, using distributed arithmetic algorithms
    Distributed Arithmetic FIR Filter Generator
  • Divider IP Core

    IP Core

    Divider IP Core

    The Lattice Divider IP core uses a non-restoring division algorithm to implement the integer division operation.
    Divider IP Core
  • Block Convolutional Encoder

    IP Core

    Block Convolutional Encoder

    Parameterizable core for convolutional encoding of continuous or burst input data streams
    Block Convolutional Encoder
  • Block Viterbi Decoder

    IP Core

    Block Viterbi Decoder

    Archived IP Core supporting LatticeECP2/M, LatticeXP2 and LatticeECP3 FPGAs - For reference only
    Block Viterbi Decoder
  • Cascaded Integrator-Comb (CIC) Filter

    IP Core

    Cascaded Integrator-Comb (CIC) Filter

    Widely parameterizable CIC filter that supports multiple channels with run-time programmable rates and differential delay parameters (aka Hogenauer Filter).
    Cascaded Integrator-Comb (CIC) Filter
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