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  • CertusPro-NX Voice and Vision Machine Learning Board

    Board

    CertusPro-NX Voice and Vision Machine Learning Board

    Design AI use cases for the Edge quickly! This board along with the Lattice sensAI solution stack provide the tools for developing vision and audio-based AI applications.
    CertusPro-NX 
    Machine Learning/AI, DSP, PMOD, Camera, Lattice sensAI, Space, Automotive 
    CertusPro-NX Voice and Vision Machine Learning Board
  • eUSB 3.1 FMC

    Board

    eUSB 3.1 FMC

    eUSB 3.1 FMC board is to validate USB 3.1 functionality with FPGA’s inbuilt serial transceivers. It has ULPI PHY chip to validate USB 2.0 functionality.
    CrossLink-NX 
    FMC, Data Compression, DSP, USB Type-C, USB3, Camera, Image Processing, Video Tx/Rx 
    eUSB 3.1 FMC
  • FFT Compiler IP Core

    IP Core

    FFT Compiler IP Core

    The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.
    ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, Certus-NX, CertusPro-NX, MachXO5-NX, CrossLink-NX, Avant-E 
    DSP IP Suite, Value IP Suite, Data Communication, DSP, Guidance Systems, Automotive 
    FFT Compiler IP Core
  • FIR Filter Generator

    IP Core

    FIR Filter Generator

    Highly configurable, multi-channel FIR filter. Supports up to 256 channels each with 2048 taps. Input and coefficient widths from 4 to 32 bits.
    ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX 
    DSP, DSP IP Suite, Value IP Suite, Guidance Systems, Automotive 
    FIR Filter Generator
  • Coordinate Rotational Digital Computer (CORDIC) IP Core

    IP Core

    Coordinate Rotational Digital Computer (CORDIC) IP Core

    The Lattice CORDIC IP uses full internal precision while allowing variable output precision with several choices for rounding.
    ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeSC/M, LatticeXP2, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E, CrossLink-NX 
    DSP, DSP IP Suite, Automotive 
    Coordinate Rotational Digital Computer (CORDIC) IP Core
  • 2D Scaler IP Core

    IP Core

    2D Scaler IP Core

    Highly-configurable design to convert input video frames of one size to output video frames of a different size
    ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, Certus-NX, CertusPro-NX, MachXO5-NX 
    DSP IP Suite, Image Processing, Video Bridge, Video IP Suite, DSP, Lattice mVision, Defense, UAVs, Automotive 
    2D Scaler IP Core
  • JESD204B IP Core

    IP Core

    JESD204B IP Core

    Supports ADC/DAC to FPGA in both an Rx and/or a Tx core. The Rx and Tx cores can each be generated separately and with different parameters.
    ECP5 / ECP5-5G, LatticeECP3 
    ADC/DAC, Connectivity IP Suite, DSP, SDR 
    JESD204B IP Core
  • Numerically Controlled Oscillator

    IP Core

    Numerically Controlled Oscillator

    Also called a Direct Digital Synthesizer (DDS). Supports multiple channels and a Quadrature Amplitude Modulation (QAM) mode, plus other usual configurations
    LatticeECP3, LatticeECP2/M, LatticeSC/M, LatticeXP2 
    DSP, DSP IP Suite 
    Numerically Controlled Oscillator
  • 2D FIR Filter

    IP Core

    2D FIR Filter

    Performs real-time 2D convolution of windowed portions of incoming video frames with coefficient matrices held in internal memory
    LatticeECP3, LatticeECP2/M, LatticeXP2 
    Data Communication, DSP, Image Processing, Video IP Suite 
    2D FIR Filter
  • Median Filter

    IP Core

    Median Filter

    Popular method of noise removal in signal processing. Supports many video frame sizes.
    LatticeECP3, LatticeECP2/M, LatticeXP2 
    DSP, Image Processing, Video IP Suite 
    Median Filter
  • 8-bit Correlator

    IP Core

    8-bit Correlator

    Correlates an incoming data stream to a stored binary pattern called a code / coefficient sequence. Configure to 8 bit width, 256 channels, 2048 taps and more.
    LatticeECP2/M, LatticeSC/M, LatticeXP2 
    Data Communication, DSP 
    8-bit Correlator
  • Interleaver/De-Interleaver

    IP Core

    Interleaver/De-Interleaver

    Supports rectangular block type and convolutional architectures. Rectangular interleaving arranges the input data row-wise in a matrix
    LatticeECP3, LatticeECP2/M, LatticeXP2, LatticeSC/M 
    DSP, DSP IP Suite 
    Interleaver/De-Interleaver
  • JESD207 IP

    IP Core

    JESD207 IP

    Implements baseband (BB) side data and control plane paths to connect to a radio front-end (RF) transceiver device with integrated ADC and DAC.
    LatticeECP3 
    ADC/DAC, CFR, CPRI, Data Communication, DSP, DUC 
    JESD207 IP
  • Distributed Arithmetic FIR Filter Generator

    IP Core

    Distributed Arithmetic FIR Filter Generator

    Implements a highly configurable, multi-channel DA-FIR filter, using distributed arithmetic algorithms
    LatticeECP3, LatticeECP2/M, LatticeXP2 
    Data Communication, DSP, DSP IP Suite, Defense 
    Distributed Arithmetic FIR Filter Generator
  • Divider IP Core

    IP Core

    Divider IP Core

    The Lattice Divider IP core uses a non-restoring division algorithm to implement the integer division operation.
    LatticeECP3, LatticeXP2, LatticeECP2/M, Certus-NX, CertusPro-NX, MachXO5-NX, CrossLink-NX, Avant-E 
    DSP, DSP IP Suite, Automotive 
    Divider IP Core
  • Block Convolutional Encoder

    IP Core

    Block Convolutional Encoder

    Parameterizable core for convolutional encoding of continuous or burst input data streams
    LatticeXP2, LatticeECP2/M, LatticeECP3 
    Data CODEC, Data Communication, DSP, DSP IP Suite 
    Block Convolutional Encoder
  • Block Viterbi Decoder

    IP Core

    Block Viterbi Decoder

    Parameterizable decoding different combinations of convolutionally encoded sequences.
    LatticeECP2/M, LatticeXP2, LatticeECP3 
    Data CODEC, Data Communication, DSP, DSP IP Suite 
    Block Viterbi Decoder
  • Cascaded Integrator-Comb (CIC) Filter

    IP Core

    Cascaded Integrator-Comb (CIC) Filter

    Widely parameterizable CIC filter that supports multiple channels with run-time programmable rates and differential delay parameters (aka Hogenauer Filter).
    LatticeECP2/M, LatticeSC/M, LatticeXP2, LatticeECP3 
    Data Communication, DSP, DSP IP Suite 
    Cascaded Integrator-Comb (CIC) Filter
  • LMS (Least Mean Square) Adaptive Filter

    Reference Design

    LMS (Least Mean Square) Adaptive Filter

    Consists of two main functional blocks - a FIR filter and the LMS algorithm.
    LatticeECP3 
    DSP 
    LMS (Least Mean Square) Adaptive Filter
  • JESD204A IP Core

    IP Core

    JESD204A IP Core

    Supports ADC/DAC to FPGA in both an Rx and/or a Tx core. The Rx and Tx cores can each be generated separately and with different parameters.
    LatticeECP3 
    ADC/DAC, DSP, SDR 
    JESD204A IP Core
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