Lattice Solutions

IP Core

FFT Compiler IP Core

The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, Certus-NX, CertusPro-NX, MachXO5-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X 

Data Communication, DSP, Guidance Systems, Automotive, DSP Bundle, SDR 

IP Core

FIR Filter Generator IP Core

This IP core is a widely configurable, multi-channel FIR filter, implemented using high performance sysDSP™ blocks available in Lattice devices.

ECP5 / ECP5-5G, LatticeECP3, LatticeXP2, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E, Avant-G, Avant-X 

DSP, Guidance Systems, Automotive, DSP Bundle, SDR 

IP Core

​​JESD204B IP Core​

​​The Lattice JESD204B IP Core is a high-speed serial interface used between data converters, and the FPGA device to replace traditional interfaces.​

ECP5 / ECP5-5G, LatticeECP3, CertusPro-NX 

ADC/DAC, DSP, SDR 

Board

CertusPro-NX Voice and Vision Machine Learning Board

Design AI use cases for the Edge quickly! This board along with the Lattice sensAI solution stack provide the tools for developing vision and audio-based AI applications.

CertusPro-NX 

Machine Learning/AI, DSP, PMOD, Camera, Lattice sensAI, Space, Automotive 

IP Core

Video Scaler IP Core

The Lattice Video Scaler IP Core is used to scale up or scale down the resolution of a video stream.

CertusPro-NX, Certus-NX, CrossLink-NX 

Lattice Drive, AXI, AXI-Lite Interface, Video Scaling, Embedded Ram, DSP, DSP Bundle 

Reference Design

JESD204 ADC Reference Design

Provides designers an ideal platform for a low cost, low power and small footprint solution for FPGA based serial data acquisition and processing

LatticeECP2/M 

ADC/DAC, DSP, SDR 

Board

eUSB 3.1 FMC

eUSB 3.1 FMC board is to validate USB 3.1 functionality with FPGA’s inbuilt serial transceivers. It has ULPI PHY chip to validate USB 2.0 functionality.

CrossLink-NX 

FMC, Data Compression, DSP, USB Type-C, USB3, Camera, Image Processing, Video Tx/Rx 

IP Core

5G O-RU L-PHY & H-PHY IP Cores

​​Yongatek's L-PHY IP in Lattice CertusPro-NX FPGA: 3GPP TS38.212 Release 16 compatible, O-RAN Alliance compliant, up to 6GHz, ideal for mid-power RF apps.​

CertusPro-NX 

CFR, CPRI, CRC, Data Communication, Data Compression, DSP, DUC, IEEE1588, AXI, SPI 

IP Core

Coordinate Rotational Digital Computer (CORDIC) IP Core

The Lattice CORDIC IP uses full internal precision while allowing variable output precision with several choices for rounding.

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeSC/M, LatticeXP2, Certus-NX, CertusPro-NX, MachXO5-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X 

DSP, Automotive, DSP Bundle 

IP Core

2D Scaler IP Core

Highly-configurable design to convert input video frames of one size to output video frames of a different size

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, Certus-NX, CertusPro-NX, MachXO5-NX 

Image Processing, Video Bridge, DSP, Lattice mVision, Defense, UAVs, Automotive, DSP Bundle 

IP Core

Numerically Controlled Oscillator

Also called a Direct Digital Synthesizer (DDS). Supports multiple channels and a Quadrature Amplitude Modulation (QAM) mode, plus other usual configurations

LatticeECP3, LatticeECP2/M, LatticeSC/M, LatticeXP2 

DSP 

IP Core

2D FIR Filter

Performs real-time 2D convolution of windowed portions of incoming video frames with coefficient matrices held in internal memory

LatticeECP3, LatticeECP2/M, LatticeXP2 

Data Communication, DSP, Image Processing 

IP Core

Median Filter

Popular method of noise removal in signal processing. Supports many video frame sizes.

LatticeECP3, LatticeECP2/M, LatticeXP2 

DSP, Image Processing 

IP Core

8-bit Correlator

Correlates an incoming data stream to a stored binary pattern called a code / coefficient sequence. Configure to 8 bit width, 256 channels, 2048 taps and more.

LatticeECP2/M, LatticeSC/M, LatticeXP2 

Data Communication, DSP 

IP Core

Interleaver/De-Interleaver

Supports rectangular block type and convolutional architectures. Rectangular interleaving arranges the input data row-wise in a matrix

LatticeECP3, LatticeECP2/M, LatticeXP2, LatticeSC/M 

DSP 

IP Core

JESD207 IP

Implements baseband (BB) side data and control plane paths to connect to a radio front-end (RF) transceiver device with integrated ADC and DAC.

LatticeECP3 

ADC/DAC, CFR, CPRI, Data Communication, DSP, DUC 

IP Core

Distributed Arithmetic FIR Filter Generator

Implements a highly configurable, multi-channel DA-FIR filter, using distributed arithmetic algorithms

LatticeECP3, LatticeECP2/M, LatticeXP2 

Data Communication, DSP, Defense 

IP Core

Divider IP Core

The Lattice Divider IP core uses a non-restoring division algorithm to implement the integer division operation.

LatticeECP3, LatticeXP2, LatticeECP2/M, Certus-NX, CertusPro-NX, MachXO5-NX, CrossLink-NX, Avant-E 

DSP, Automotive, DSP Bundle 

IP Core

Block Convolutional Encoder

Parameterizable core for convolutional encoding of continuous or burst input data streams

LatticeXP2, LatticeECP2/M, LatticeECP3 

Data CODEC, Data Communication, DSP 

IP Core

Block Viterbi Decoder

Archived IP Core supporting LatticeECP2/M, LatticeXP2 and LatticeECP3 FPGAs - For reference only

LatticeECP2/M, LatticeXP2, LatticeECP3 

Data CODEC, Data Communication, DSP