Lattice Solutions

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  • FFT Compiler

    IP Core

    FFT Compiler

    Can be configured to perform forward FFT, inverse FFT (IFFT) or port selectable forward/inverse FFT. High-performance streaming and low-resource burst modes.
    FFT Compiler
  • FIR Filter Generator

    IP Core

    FIR Filter Generator

    Highly configurable, multi-channel FIR filter. Supports up to 256 channels each with 2048 taps. Input and coefficient widths from 4 to 32 bits.
    FIR Filter Generator
  • CORDIC

    IP Core

    CORDIC

    A simple and efficient algorithm to calculate hyperbolic and trigonometric functions and convert polar co-ordinates to cartesian and vice versa
    CORDIC
  • 2D Scaler

    IP Core

    2D Scaler

    Highly-configurable design to convert input video frames of one size to output video frames of a different size
    2D Scaler
  • Numerically Controlled Oscillator

    IP Core

    Numerically Controlled Oscillator

    Also called a Direct Digital Synthesizer (DDS). Supports multiple channels and a Quadrature Amplitude Modulation (QAM) mode, plus other usual configurations
    Numerically Controlled Oscillator
  • 2D FIR Filter

    IP Core

    2D FIR Filter

    Performs real-time 2D convolution of windowed portions of incoming video frames with coefficient matrices held in internal memory
    2D FIR Filter
  • Median Filter

    IP Core

    Median Filter

    Popular method of noise removal in signal processing. Supports many video frame sizes.
    Median Filter
  • 8-bit Correlator

    IP Core

    8-bit Correlator

    Correlates an incoming data stream to a stored binary pattern called a code / coefficient sequence. Configure to 8 bit width, 256 channels, 2048 taps and more.
    8-bit Correlator
  • Interleaver/De-Interleaver

    IP Core

    Interleaver/De-Interleaver

    Supports rectangular block type and convolutional architectures. Rectangular interleaving arranges the input data row-wise in a matrix
    Interleaver/De-Interleaver
  • JESD204B IP Core

    IP Core

    JESD204B IP Core

    Supports ADC/DAC to FPGA in both an Rx and/or a Tx core. The Rx and Tx cores can each be generated separately and with different parameters.
    JESD204B IP Core
  • JESD207 IP

    IP Core

    JESD207 IP

    Implements baseband (BB) side data and control plane paths to connect to a radio front-end (RF) transceiver device with integrated ADC and DAC.
    JESD207 IP
  • Distributed Arithmetic FIR Filter Generator

    IP Core

    Distributed Arithmetic FIR Filter Generator

    Implements a highly configurable, multi-channel DA-FIR filter, using distributed arithmetic algorithms
    Distributed Arithmetic FIR Filter Generator
  • Divider

    IP Core

    Divider

    A one-clock divider which completes one integer division every clock. It supports signed or unsigned inputs and provides configurable output latency.
    Divider
  • Block Convolutional Encoder

    IP Core

    Block Convolutional Encoder

    Parameterizable core for convolutional encoding of continuous or burst input data streams
    Block Convolutional Encoder
  • Block Viterbi Decoder

    IP Core

    Block Viterbi Decoder

    Parameterizable decoding different combinations of convolutionally encoded sequences.
    Block Viterbi Decoder
  • Cascaded Integrator-Comb (CIC) Filter

    IP Core

    Cascaded Integrator-Comb (CIC) Filter

    Widely parameterizable CIC filter that supports multiple channels with run-time programmable rates and differential delay parameters (aka Hogenauer Filter).
    Cascaded Integrator-Comb (CIC) Filter
  • LMS (Least Mean Square) Adaptive Filter

    Reference Design

    LMS (Least Mean Square) Adaptive Filter

    Consists of two main functional blocks - a FIR filter and the LMS algorithm.
    DSP 
    LMS (Least Mean Square) Adaptive Filter
  • JESD204A IP Core

    IP Core

    JESD204A IP Core

    Supports ADC/DAC to FPGA in both an Rx and/or a Tx core. The Rx and Tx cores can each be generated separately and with different parameters.
    JESD204A IP Core
  • TI TSW1405 & TSW1406 HDL Reference Design

    Reference Design

    TI TSW1405 & TSW1406 HDL Reference Design

    Interface the LatticeECP3 FPGA to TI TSW1405 and TSW1406 ADCs.
    TI TSW1405 & TSW1406 HDL Reference Design
  • JESD204 ADC

    Reference Design

    JESD204 ADC

    Provides designers an ideal platform for a low cost, low power and small footprint solution for FPGA based serial data acquisition and processing
    JESD204 ADC
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