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  • Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP

    Demo

    Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP

    Demo for Lattice ORAN Secure Sync show how Lattice FPGA w/ soft IPs can support tight & secure synchronization using 1588 PTP & ITU profiles for Telecom.
    Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP
  • Lattice ORAN Timing and Synchronization Kit

    Board

    Lattice ORAN Timing and Synchronization Kit

    ORAN Sync Board has 2x 10GE & 2x 1GE ports, SMA & FMC connectors for testing, demos, development, GNSS & on-board timing sources, ToD, & PPS RJ48 connectors
    Lattice ORAN Timing and Synchronization Kit
  • Lattice ORAN IEEE 1588 PTP Secure Sync Reference Design

    Reference Design

    Lattice ORAN IEEE 1588 PTP Secure Sync Reference Design

    Lattice ORAN 1.1 RD shows how to provide ultra-reliable time synchronization & phase alignment for delivering timing accuracy in 5G ORAN networks.
    Lattice ORAN IEEE 1588 PTP Secure Sync Reference Design
  • 5G O-RU L-PHY & H-PHY IP Cores

    IP Core

    5G O-RU L-PHY & H-PHY IP Cores

    ​​Yongatek's L-PHY IP in Lattice CertusPro-NX FPGA: 3GPP TS38.212 Release 16 compatible, O-RAN Alliance compliant, up to 6GHz, ideal for mid-power RF apps.​
    5G O-RU L-PHY & H-PHY IP Cores
  • Lattice Avant G70 PCIe Mini-Board

    Board

    Lattice Avant G70 PCIe Mini-Board

    Avant G70 PCIe Mini-Board with Lattice Avant-G FPGA supports AI, video & industrial use with PCIe, SFP+, FMC, MIPI, memory, clock & more high-performance tasks.
    Lattice Avant G70 PCIe Mini-Board
  • Adjustable Counter Clock

    IP Core

    Adjustable Counter Clock

    The adjustable clock IP is a counter clock that can be adjusted with offset and drift corrections to follow another clock.
    Adjustable Counter Clock
  • Time Sensitive Networking (TSN) End Node

    IP Core

    Time Sensitive Networking (TSN) End Node

    The Time Sensitive Networking (TSN) End Node IP supports scheduling, priority queues, credit shaping, cyclic forwarding and preemption.
    Time Sensitive Networking (TSN) End Node
  • Time Sensitive Networking (TSN) Network Node

    IP Core

    Time Sensitive Networking (TSN) Network Node

    Time Sensitive Networking (TSN) Switched End Node IP supports 3 Ports, scheduling, priority queues, credit shaping, redundancy, cyclic forwarding and preemption
    Time Sensitive Networking (TSN) Network Node
  • TSN-EP – TSN Ethernet Endpoint Controller

    IP Core

    TSN-EP – TSN Ethernet Endpoint Controller

    Highly flexible core supports timing synchronization (IEEE 802.1AS), traffic shaping (IEEE 802.1Qav, Qbv) and frame-preemption (IEEE 802.1Qbu, & 802.3br).
    TSN-EP – TSN Ethernet Endpoint Controller
  • IEEE 1588 Syn1588®Clock_M Core

    IP Core

    IEEE 1588 Syn1588®Clock_M Core

    Highly accurate clock synchronization compliant to the IEEE 1588 standard version 1.0 and 2.0 for Industrial Ethernet applications.
    IEEE 1588 Syn1588®Clock_M Core
  • IEEE 1588 Syn1588®Clock_S Core

    IP Core

    IEEE 1588 Syn1588®Clock_S Core

    Highly accurate clock synchronization compliant to the IEEE 1588 standard version 1.0 and 2.0 for Industrial Ethernet applications
    IEEE 1588 Syn1588®Clock_S Core
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