IEEE 1588 Syn1588®Clock_S Core

Oregano Systems LogoThe SYN1588®Clock_S IP-core provides highly accurate clock synchronization compliant to the IEEE 1588 standard version 1.0 and 2.0 for Industrial Ethernet applications. It provides a high resolution, high accuracy hardware clock which uses a 96-bit wide adder based clock architecture allowing supporting input clock frequencies in the range of 10 – 200 MHz.

Furthermore, the SYN1588 Clock_S comprises an MII-Scanner unit, which scans all Ethernet traffic in search for IEEE 1588 synchronization packets. Upon detection of any such packet it draws a 96-bit wide time stamp from the local clock and copies it together with status and identification data into a time-stamp FIFO.

Evaluation and Licensing Terms

Please contact Oregano directly at: http://www.oregano.at

Features

  • Supports 10/100 Mbit/s half & full duplex modes
  • Delivered with PTP Version 1.0 and version 2.0 stack (Linux or Windows®)
  • Supports SPI cascade and independent slave mode
  • SPI data rates up to 20 Mbit/sec
  • 16-bit SPI data transfers, 32 bit interface to the internal SPI controller
  • 1 pps output
  • 1 period timer output with a period ranging from 14,000 sec down to 200 nsec.
  • 1 event input which draws a time stamp and stores it in the time stamp FIFO.
  • Events may be processed at a burst rate of 1 MHz
  • 1 trigger output signal which may be used to generate a signal transition at a given point in time
  • All event, period, and trigger signals are strictly synchronous to the internal high accuracy clock
  • Delivered with test bench, 100% code coverage guaranteed
  • Optional support of GPS timing receivers
  • RMII Interface option available upon request

Applications

  • Test and Measurement
  • Industrial Automation and Control
  • Telecom
  • Military
  • Power Industry

Jump to

Block Diagram

Performance and Size

The following are typical performance and utilization results.

Lattice Device Speed grade Slices LUTs REGs EBRs fMAX (MHz)
XP -7 1668 1954 1726 4 75
XP2 -7 1552 1968 1591 4 125

Ordering Information

This IP core is supported and sold by Oregano Systems, contact Oregano Systems at contact@oregano.at or visit their website at www.oreganosystems.at for more information.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Oregano syn1588 VIP Dual HP Brief Data Sheet
1.1 4/25/2011 PDF 104.1 KB
Oregano syn1588 VIP Dual Brief Data Sheet
1.1 4/25/2011 PDF 83.4 KB
Oregano syn1588 VIP Brief Data Sheet
1.6 5/2/2011 PDF 142.5 KB
Oregano IEEE 1588 Syn1588 Data Sheet
The SYN1588®Clock_S IP-core provides highly accurate clock synchronization compliant to the IEEE 1588 standard version 1.0 and 2.0 for industrial Ethernet applications.
12/3/2007 PDF 49.9 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.