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General Purpose
Includes all ECP
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Narrow Your Results
Solution Type
Boards
Demos
IP Cores (27)
Reference Designs
Device Support
Avant-E (3)
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CrossLink-NX (6)
ECP5 / ECP5-5G (17)
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MachXO5-NX (1)
Tags
16PP194 and H009 (1)
AHB (4)
AHB-Lite (3)
AMBA (1)
APB (1)
ARM (2)
Audio AI (1)
Automotive (1)
AWB (1)
AXI (27)
AXI-Lite Interface (4)
AXI-Stream (1)
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CCM (1)
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Connectivity IP Suite (1)
Cyber Authentication (2)
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DDR Memories (1)
DDR SDRAM (1)
Debayer (1)
Defense (1)
DisplayPort (1)
DO-254 and DO-178 (2)
DSP (1)
Embedded Ram (13)
Encryption (2)
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FMC (2)
GPIO Control (1)
IEEE 802.3 (2)
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IEEE802.1 (2)
Image Processing (11)
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Object Detection (1)
Object Identification (1)
Object Tracking (1)
Post-Quantum Cryptography (2)
RGB (1)
RISC-V (15)
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Soft Processor (4)
SPI (2)
Time Synchronization (1)
TSN (2)
UART (1)
ULPI (2)
USB Type-C (1)
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USB3 (1)
Value IP Suite (1)
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Video Tx/Rx (10)
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Providers
Bluespec (1)
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Etron (1)
Lattice (4)
NetTimeLogic (3)
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PQShield Ltd. (2)
Sital (2)
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Clear All
IP Core
Image Signal Processing IP Cores Suite
The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.
CrossLink-NX
,
Certus-NX
,
CertusPro-NX
,
Avant-E
AXI
,
AXI-Stream
,
AXI-Lite Interface
,
AWB
,
Camera
,
CCM
,
CFA Interpolation
,
Debayer
,
Image Processing
,
Image Signal Processing
,
Lattice mVision
,
RGB
IP Core
Video Scaler IP Core
The Lattice Video Scaler IP Core is used to scale up or scale down the resolution of a video stream.
CertusPro-NX
,
Certus-NX
,
CrossLink-NX
Lattice Drive
,
AXI
,
AXI-Lite Interface
,
Video Scaling
,
Embedded Ram
,
DSP
IP Core
AXI Register Slice IP Core
The AXI Register Slice connects the AXI subordinate to the AXI manager by introducing pipeline stages in between to close the timing in critical paths.
Avant-E
,
CertusPro-NX
AXI
,
AXI-Lite Interface
,
Lattice Propel
,
Lattice Radiant
IP Core
eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)
This IP core solution uses the CL-NX FPGA’s built-in transceiver for USB 3.1 and ULPI PHY for USB 2.0. It supports SuperSpeed, High Speed and Full Speed modes.
CrossLink-NX
ARM
,
RISC-V
,
Soft Processor
,
FMC
,
AHB
,
AHB-Lite
,
AXI
,
USB Type-C
,
USB3
,
USB2
,
ULPI
IP Core
RISC-V Single Core Linux (SCL) Processor
RISC-V Single Core Linux processor includes everything required for running Linux on Lattice FPGAs and supports the RV32IMAC and RV32GC architecture.
CertusPro-NX
RISC-V
,
Soft Processor
,
DDR Memories
,
AHB
,
AHB-Lite
,
AMBA
,
AXI
,
GPIO Control
,
UART
IP Core
USB 2.0 Device Controller IP Core (USB20SF)
USB20SF IP core provides FIFO interface for Data Endpoints while AHB Lite interface for Control Endpoint. This IP core supports High Speed and Full Speed modes
CrossLink-NX
ARM
,
RISC-V
,
Soft Processor
,
FMC
,
AHB
,
AHB-Lite
,
AXI
,
Camera
,
ULPI
,
USB2
IP Core
Tri-Speed Ethernet MAC IP Core
The TSEMAC IP core have the logic, interfacing & clocking infra to ably integrate an external industry-standard Ethernet PHY with an internal processor
ECP5 / ECP5-5G
,
LatticeECP3
,
LatticeECP2/M
,
LatticeXP2
,
LatticeSC/M
,
CrossLink-NX
,
Certus-NX
,
CertusPro-NX
,
MachXO5-NX
,
Avant-E
Connectivity IP Suite
,
Data Communication
,
Ethernet
,
Value IP Suite
,
Defense
,
Automotive
,
APB
,
AXI
,
AXI-Lite Interface
,
AHB
IP Core
Ikva ML Accelerator IP Core
Powerful, scalable ML accelerator supporting 8-bit CNNs and 1-bit Binarized Neural Networks (BNNs), a rich software stack and computer vision models.
CrossLink-NX
Audio AI
,
Machine Learning/AI
,
Object Counting
,
Object Detection
,
Object Identification
,
Object Tracking
,
RISC-V
,
AXI
IP Core
RPC DRAM Controller
Implements an FPGA-based RPC DRAM Memory Controller. Up to 400 MHz / 800 Mbps with memory data path widths of -16, and -32 bits - AXI interface.
ECP5 / ECP5-5G
DDR SDRAM
,
AXI
IP Core
Adjustable Counter Clock
The adjustable clock IP is a counter clock that can be adjusted with offset and drift corrections to follow another clock.
Certus-NX
,
CertusPro-NX
,
ECP5 / ECP5-5G
IEEE1588
,
AXI
,
Time Synchronization
IP Core
DPC CCM – Color correction
DPC CCM is designed to reduce the difference between the spectral characteristics of an image sensor and the spectral response of the human eye.
ECP5 / ECP5-5G
,
CrossLink
RISC-V
,
AXI
,
Image Processing
,
Video Tx/Rx
,
Embedded Ram
IP Core
DPC Color Conversion
DPC Color Conversion allows real-time conversion of the RGB colour space into the YCbCr colour space.
ECP5 / ECP5-5G
,
CrossLink
RISC-V
,
AXI
,
Image Processing
,
Video Tx/Rx
,
Embedded Ram
IP Core
DPC Convolution 3x3
DPC Conv3x3 applies a kernel to a video stream, in real time, in order to obtain spatial filtering such as Sobel, Gaussian, Laplacian and more.
ECP5 / ECP5-5G
,
CrossLink
RISC-V
,
AXI
,
Image Processing
,
Video Tx/Rx
,
Embedded Ram
IP Core
DPC Debayer
DPC Debayer reconstructs RGB images, in real time, from RAW data captured by an image sensor.
ECP5 / ECP5-5G
,
CrossLink
RISC-V
,
AXI
,
Image Processing
,
Video Tx/Rx
,
Embedded Ram
IP Core
DPC Defective Pixel Correction
DPC Defective detects and corrects defective pixels in applications with a Bayer pattern image sensor.
ECP5 / ECP5-5G
,
CrossLink
RISC-V
,
AXI
,
Image Processing
,
Video Tx/Rx
,
Embedded Ram
IP Core
DPC Gamma RGB
DPC Gamma RGB is the IP dedicated to correcting, in real time, the gamma transformation curve of an incoming video stream.
ECP5 / ECP5-5G
,
CrossLink
RISC-V
,
AXI
,
Image Processing
,
Video Tx/Rx
,
Embedded Ram
IP Core
DPC HDR
DPC HDR obtains an HDR (High Dynamic Range) output stream from two separate input streams (high exposure and low exposure).
ECP5 / ECP5-5G
,
CrossLink
RISC-V
,
AXI
,
Image Processing
,
Video Tx/Rx
,
Embedded Ram
IP Core
DPC Statistics RGB
DPC Statistics RGB provides, for each frame, the histograms of the R, G and B channels.
ECP5 / ECP5-5G
,
CrossLink
RISC-V
,
AXI
,
Image Processing
,
Video Tx/Rx
,
Embedded Ram
IP Core
DPC Statistics YCbCr
DPC Statistics YCbCr provides, for each frame, the histograms of the Y, Cb and Cr channels.
ECP5 / ECP5-5G
,
CrossLink
RISC-V
,
AXI
,
Image Processing
,
Video Tx/Rx
,
Embedded Ram
IP Core
DPC Subsampler 4:2:2
DPC Subsampler422 is a simple IP block for real-time conversion of a YCbCr 4:4:4 video stream to a YCbCr 4:2:2 stream.
ECP5 / ECP5-5G
,
CrossLink
RISC-V
,
AXI
,
Image Processing
,
Video Tx/Rx
,
Embedded Ram
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