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  • eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)

    IP Core

    eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)

    This IP core solution uses the CL-NX FPGA’s built-in transceiver for USB 3.1 and ULPI PHY for USB 2.0. It supports SuperSpeed, High Speed and Full Speed modes.
    eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)
  • USB 2.0 Device Controller IP Core (USB20SF)

    IP Core

    USB 2.0 Device Controller IP Core (USB20SF)

    USB20SF IP core provides FIFO interface for Data Endpoints while AHB Lite interface for Control Endpoint. This IP core supports High Speed and Full Speed modes
    USB 2.0 Device Controller IP Core (USB20SF)
  • Ikva ML Accelerator IP Core

    IP Core

    Ikva ML Accelerator IP Core

    Powerful, scalable ML accelerator supporting 8-bit CNNs and 1-bit Binarized Neural Networks (BNNs), a rich software stack and computer vision models.
    Ikva ML Accelerator IP Core
  • RPC DRAM Controller

    IP Core

    RPC DRAM Controller

    Implements an FPGA-based RPC DRAM Memory Controller. Up to 400 MHz / 800 Mbps with memory data path widths of -16, and -32 bits - AXI interface.
    RPC DRAM Controller
  • Adjustable Counter Clock

    IP Core

    Adjustable Counter Clock

    The adjustable clock IP is a counter clock that can be adjusted with offset and drift corrections to follow another clock.
    Adjustable Counter Clock
  • DPC CCM – Color correction

    IP Core

    DPC CCM – Color correction

    DPC CCM is designed to reduce the difference between the spectral characteristics of an image sensor and the spectral response of the human eye.
    DPC CCM – Color correction
  • DPC Color Conversion

    IP Core

    DPC Color Conversion

    DPC Color Conversion allows real-time conversion of the RGB colour space into the YCbCr colour space.
    DPC Color Conversion
  • DPC Convolution 3x3

    IP Core

    DPC Convolution 3x3

    DPC Conv3x3 applies a kernel to a video stream, in real time, in order to obtain spatial filtering such as Sobel, Gaussian, Laplacian and more.
    DPC Convolution 3x3
  • DPC Debayer

    IP Core

    DPC Debayer

    DPC Debayer reconstructs RGB images, in real time, from RAW data captured by an image sensor.
    DPC Debayer
  • DPC Defective Pixel Correction

    IP Core

    DPC Defective Pixel Correction

    DPC Defective detects and corrects defective pixels in applications with a Bayer pattern image sensor.
    DPC Defective Pixel Correction
  • DPC Gamma RGB

    IP Core

    DPC Gamma RGB

    DPC Gamma RGB is the IP dedicated to correcting, in real time, the gamma transformation curve of an incoming video stream.
    DPC Gamma RGB
  • DPC HDR

    IP Core

    DPC HDR

    DPC HDR obtains an HDR (High Dynamic Range) output stream from two separate input streams (high exposure and low exposure).
    DPC HDR
  • DPC Statistics RGB

    IP Core

    DPC Statistics RGB

    DPC Statistics RGB provides, for each frame, the histograms of the R, G and B channels.
    DPC Statistics RGB
  • DPC Statistics YCbCr

    IP Core

    DPC Statistics YCbCr

    DPC Statistics YCbCr provides, for each frame, the histograms of the Y, Cb and Cr channels.
    DPC Statistics YCbCr
  • DPC Subsampler 4:2:2

    IP Core

    DPC Subsampler 4:2:2

    DPC Subsampler422 is a simple IP block for real-time conversion of a YCbCr 4:4:4 video stream to a YCbCr 4:2:2 stream.
    DPC Subsampler 4:2:2
  • Time Sensitive Networking (TSN) End Node

    IP Core

    Time Sensitive Networking (TSN) End Node

    The Time Sensitive Networking (TSN) End Node IP supports scheduling, priority queues, credit shaping, cyclic forwarding and preemption.
    Time Sensitive Networking (TSN) End Node
  • Time Sensitive Networking (TSN) Network Node

    IP Core

    Time Sensitive Networking (TSN) Network Node

    Time Sensitive Networking (TSN) Switched End Node IP supports 3 Ports, scheduling, priority queues, credit shaping, redundancy, cyclic forwarding and preemption
    Time Sensitive Networking (TSN) Network Node
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