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  • PCI Express for Avant FPGAs

    IP Core

    PCI Express for Avant FPGAs

    The Lattice PCIe X8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express for Avant FPGAs
  • USB 2.0/3.2 IP Core

    IP Core

    USB 2.0/3.2 IP Core

    Lattice USB 2.0/3.2 IP Core provides a solution to interface with a USB host and can be targeted to the Lattice CrossLink-NX FPGA Devices.
    USB 2.0/3.2 IP Core
  • AXI4 Interconnect Module

    IP Core

    AXI4 Interconnect Module

    AXI4 Interconnect is a flexible, versatile, and easy-to-use IP with high-performance and low-latency interconnect fabric for AMBA 4 AXI/AXI-lite based systems.
    AXI4 Interconnect Module
  • AXI4 Multi Port Bridge for Memory Controller IP Core

    IP Core

    AXI4 Multi Port Bridge for Memory Controller IP Core

    The AXI4 Multi Port Bridge for Memory Controller (MPMC) IP connects multiple external managers to a single memory controller.
    AXI4 Multi Port Bridge for Memory Controller IP Core
  • Image Signal Processing IP Cores Suite

    IP Core

    Image Signal Processing IP Cores Suite

    The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.
    Image Signal Processing IP Cores Suite
  • Video Scaler IP Core

    IP Core

    Video Scaler IP Core

    The Lattice Video Scaler IP Core is used to scale up or scale down the resolution of a video stream.
    Video Scaler IP Core
  • AXI Register Slice IP Core

    IP Core

    AXI Register Slice IP Core

    The AXI Register Slice connects the AXI subordinate to the AXI manager by introducing pipeline stages in between to close the timing in critical paths.
    AXI Register Slice IP Core
  • eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)

    IP Core

    eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)

    This IP core solution uses the CL-NX FPGA’s built-in transceiver for USB 3.1 and ULPI PHY for USB 2.0. It supports SuperSpeed, High Speed and Full Speed modes.
    eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)
  • RISC-V Single Core Linux (SCL) Processor

    IP Core

    RISC-V Single Core Linux (SCL) Processor

    RISC-V Single Core Linux processor includes everything required for running Linux on Lattice FPGAs and supports the RV32IMAC and RV32GC architecture.
    RISC-V Single Core Linux (SCL) Processor
  • USB 2.0 Device Controller IP Core (USB20SF)

    IP Core

    USB 2.0 Device Controller IP Core (USB20SF)

    USB20SF IP core provides FIFO interface for Data Endpoints while AHB Lite interface for Control Endpoint. This IP core supports High Speed and Full Speed modes
    USB 2.0 Device Controller IP Core (USB20SF)
  • 5G O-RU L-PHY & H-PHY IP Cores

    IP Core

    5G O-RU L-PHY & H-PHY IP Cores

    ​​Yongatek's L-PHY IP in Lattice CertusPro-NX FPGA: 3GPP TS38.212 Release 16 compatible, O-RAN Alliance compliant, up to 6GHz, ideal for mid-power RF apps.​
    5G O-RU L-PHY & H-PHY IP Cores
  • Tri-Speed Ethernet MAC IP Core

    IP Core

    Tri-Speed Ethernet MAC IP Core

    The TSEMAC IP core have the logic, interfacing & clocking infra to ably integrate an external industry-standard Ethernet PHY with an internal processor
    Tri-Speed Ethernet MAC IP Core
  • Ikva ML Accelerator IP Core

    IP Core

    Ikva ML Accelerator IP Core

    Powerful, scalable ML accelerator supporting 8-bit CNNs and 1-bit Binarized Neural Networks (BNNs), a rich software stack and computer vision models.
    Ikva ML Accelerator IP Core
  • RPC DRAM Controller

    IP Core

    RPC DRAM Controller

    Implements an FPGA-based RPC DRAM Memory Controller. Up to 400 MHz / 800 Mbps with memory data path widths of -16, and -32 bits - AXI interface.
    RPC DRAM Controller
  • Adjustable Counter Clock

    IP Core

    Adjustable Counter Clock

    The adjustable clock IP is a counter clock that can be adjusted with offset and drift corrections to follow another clock.
    Adjustable Counter Clock
  • DPC CCM – Color correction

    IP Core

    DPC CCM – Color correction

    DPC CCM is designed to reduce the difference between the spectral characteristics of an image sensor and the spectral response of the human eye.
    DPC CCM – Color correction
  • DPC Color Conversion

    IP Core

    DPC Color Conversion

    DPC Color Conversion allows real-time conversion of the RGB colour space into the YCbCr colour space.
    DPC Color Conversion
  • DPC Convolution 3x3

    IP Core

    DPC Convolution 3x3

    DPC Conv3x3 applies a kernel to a video stream, in real time, in order to obtain spatial filtering such as Sobel, Gaussian, Laplacian and more.
    DPC Convolution 3x3
  • DPC Debayer

    IP Core

    DPC Debayer

    DPC Debayer reconstructs RGB images, in real time, from RAW data captured by an image sensor.
    DPC Debayer
  • DPC Defective Pixel Correction

    IP Core

    DPC Defective Pixel Correction

    DPC Defective detects and corrects defective pixels in applications with a Bayer pattern image sensor.
    DPC Defective Pixel Correction
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