莱迪思解决方案

IP Core

Image Signal Processing IP Cores Suite

The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.

CrossLink-NX, Certus-NX, CertusPro-NX, Avant-E, Avant-G, Avant-X, Certus-N2 

AXI, AXI-Stream, AXI-Lite Interface, AWB, Camera, CCM, CFA Interpolation, Debayer, Image Processing, Image Signal Processing, Lattice mVision, RGB, Defense, Avionics 

IP Core

USB 2.0/3.2 IP核

莱迪思USB 2.0/3.2 IP核提供了一种连接USB主机的解决方案，适用于莱迪思CrossLink-NX FPGA最新器件。

CrossLink-NX 

USB, USB2, USB3, AHB, AHB-L, AHB-Lite, AXI, I2C, SPI, JTAG, LVDS, SLVS, FTDI 

IP Core

PCI Express for Avant and Nexus 2 FPGAs

The Lattice PCIe X8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.

Avant-G, Avant-X, Certus-N2 

AXI, AHB, AHB-Lite, RTL, PCIe, Bus Controllers, Defense, Automotive, Lattice Avant, PCI, PCIe Bundle, SDR, Avionics 

演示

Multi Object Detection Demonstration

Enabling real-time detection, classification, and tracking of multiple objects in diverse environments.

CertusPro-NX 

D-PHY, OSPI, PCIe, USB, SPI, I2C, AXI, APB, Lattice sensAI 

IP Core

AXI4 Interconnect IP Core

AXI4 Interconnect is a flexible, versatile, and easy-to-use IP with high-performance and low-latency interconnect fabric for AMBA 4 AXI/AXI-lite based systems.

Certus-N2, Avant-E, Avant-G, Avant-X, CrossLink-NX, MachXO5-NX, Certus-NX, CertusPro-NX, ECP5 / ECP5-5G, LatticeECP3 

AMBA, AXI4, AXI, AXI-Lite Interface, Lattice Avant 

IP Core

AXI4 Multi Port Bridge for Memory Controller IP Core

The AXI4 Multi Port Bridge for Memory Controller (MPMC) IP connects multiple external managers to a single memory controller.

Avant-E, Avant-G, Avant-X, CertusPro-NX 

AXI4, Memory Controller, AXI 

演示

Defect Detection Demonstration

Enabling real-time detection and classification of defects in manufacturing, assembly, and inspection processes.

CertusPro-NX 

PCIe, USB, SPI, I2C, AXI, APB, D-PHY, OSPI, Lattice sensAI 

Reference Design

POS PHY Level 3链路

Enables real-time detection, classification, and tracking of multiple objects in images and video streams at the edge.

CertusPro-NX 

D-PHY, OSPI, PCIe, USB, SPI, I2C, AXI, APB, Lattice sensAI 

Reference Design

POS PHY Level 3链路

Enables real-time identification and classification of defects in manufacturing, assembly, and inspection processes at the edge.

CertusPro-NX 

D-PHY, OSPI, PCIe, USB, SPI, I2C, AXI, APB, Lattice sensAI 

IP Core

视频缩放器IP核

莱迪思视频缩放器IP核用于放大或缩小视频流的分辨率。

Certus-N2, Avant-E, Avant-G, Avant-X, CrossLink-NX, Certus-NX, CertusPro-NX, ECP5 / ECP5-5G, LatticeECP3, LatticeXP2, MachXO5-NX 

Lattice Drive, AXI, AXI-Lite Interface, Video Scaling, Embedded Ram, DSP, DSP Bundle 

IP Core

SPI Sub IP Core

The SPI Sub IP Core is a versatile, efficient solution for SPI communication between an FPGA and a microcontroller, SoC, or another FPGA.

Avant-E, Avant-G, Avant-X, MachXO5-NX, CertusPro-NX, Certus-NX, MachXO3, ECP5 / ECP5-5G 

AXI, SPI 

IP Core

AXI Register Slice IP Core

The AXI Register Slice connects the AXI subordinate to the AXI manager by introducing pipeline stages in between to close the timing in critical paths.

LatticeECP3, ECP5 / ECP5-5G, CrossLink-NX, Certus-NX, MachXO5-NX, CertusPro-NX, Avant-E, Certus-N2 

AXI, AXI-Lite Interface, Lattice Propel, Lattice Radiant 

IP Core

RISC-V Single Core Linux (SCL) Processor

RISC-V Single Core Linux processor includes everything required for running Linux on Lattice FPGAs and supports the RV32IMAC and RV32GC architecture.

CertusPro-NX 

RISC-V, Soft Processor, DDR Memories, AHB, AHB-Lite, AMBA, AXI, GPIO Control, UART 

IP Core

USB 2.0 Device Controller IP Core (USB20SF)

USB20SF IP core provides FIFO interface for Data Endpoints while AHB Lite interface for Control Endpoint. This IP core supports High Speed and Full Speed modes

CrossLink-NX, CertusPro-NX 

ARM, RISC-V, Soft Processor, FMC, AHB, AHB-Lite, AXI, Camera, ULPI, USB2 

IP Core

​​USB 3.2 Gen 1 Device Controller IP Core (USB32SF)​

This IP core solution uses the FPGA’s built-in transceiver for USB 3.2 and ULPI PHY for USB 2.0. It supports SuperSpeed, High Speed and Full Speed modes.

CrossLink-NX, CertusPro-NX 

ARM, RISC-V, Soft Processor, FMC, AHB, AHB-Lite, AXI, USB Type-C, USB3, Camera, Image Processing, MIPI 

IP Core

5G O-RU L-PHY & H-PHY IP Cores

​​Yongatek's L-PHY IP in Lattice CertusPro-NX FPGA: 3GPP TS38.212 Release 16 compatible, O-RAN Alliance compliant, up to 6GHz, ideal for mid-power RF apps.​

CertusPro-NX 

CFR, CPRI, CRC, Data Communication, Data Compression, DSP, DUC, IEEE1588, AXI, SPI 

IP Core

三倍速以太网MAC

在主机处理器和以太网之间发送和接收数据。符合IEEE 802.3标准。支持10/100/1000 Mbps传输速率。

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, LatticeSC/M, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E, Avant-G, Avant-X, Certus-N2 

Data Communication, Ethernet, Defense, Automotive, APB, AXI, AXI-Lite Interface, AHB, Ethernet Bundle 

IP Core

RPC DRAM控制器

实现基于FPGA的RPC DRAM存储控制器。高达400 MHz/800 Mbps，存储数据路径宽度为16位和32位AXI接口。

ECP5 / ECP5-5G 

DDR SDRAM, AXI 

IP Core

Adjustable Counter Clock

The adjustable clock IP is a counter clock that can be adjusted with offset and drift corrections to follow another clock.

Certus-NX, CertusPro-NX, ECP5 / ECP5-5G 

IEEE1588, AXI, Time Synchronization 

IP Core

Time Sensitive Networking (TSN) End Node

The Time Sensitive Networking (TSN) End Node IP supports scheduling, priority queues, credit shaping, cyclic forwarding and preemption.

Certus-NX, CertusPro-NX, ECP5 / ECP5-5G 

IEEE1588, IEEE802.1, Data Communication, Ethernet, IEEE 802.3, AXI, TSN