SPI Sub IP Core

P2L2’s Sub IP Core Enables Maximum SPI Speed for Low-cost FPGA

The Serial Peripheral Interface (SPI) is a popular choice for connecting an FPGA to a microcontroller or a System-on-Chip (SoC), especially in low-cost applications. Most microcontrollers, in the role of the SPI main node (commonly referred to as master mode), offer SPI data rates of 50 MHz or higher. To enable communication with the FPGA, an SPI subnode IP core is used within the FPGA. Unlike other SPI IP cores on the market, which require an FPGA system clock frequency that is four times higher than the SPI clock frequency, this core operates efficiently even when the FPGA system clock frequency is as low as 0.6 times the SPI clock frequency. This is made possible by an advanced synchronization scheme implemented in the IP design.

Features

  • Resource efficient connection of FPGA to a micro-controller or SoC
  • Allows for low-cost FPGA at high SPI data rates
  • Proven in several customer products
  • Low resource footprint perfectly fitting low-cost applications
  • Advanced synchronization scheme enables SPI clock frequency up to 1.66×system clock frequency: SPI clock rate can be higher than FPGA system clock rate
  • Streaming interfaces to logic (AXI or Avalon ST)
  • Optional CRC16 or CRC32 calculation
  • Optional automated SPI frame/packet enumeration
  • Configurable SPI clock phase and polarity