Space Solutions

Advancing the future of commercial space systems with Lattice FPGAs

Related Products

With the rapid growth of low-earth orbit satellites, the space industry is undergoing an unprecedented expansion to offer new capabilities and services. Lattice leverages the experience to build power efficient, small form factor and reliable FPGAs to deliver a scalable portfolio of inherently radiation tolerant FPGAs in support of the emerging field of small satellites for governments and businesses worldwide.

Lattice FPGA reliability and quality have been independently verified by multiple agencies to meet the performance, reliability and lifecycle demands of space systems. To obtain heavy-ion and Total Ionization Dose test reports and other relevant documents, contact Lattice sales.

  • Flexibility to enable in-flight reprogrammable systems coupled with low power operation gives satellite operators the ability to improve mission responsiveness and real-time processing.
  • Lowest soft error rate (SER) in its class and highest latch-up immunity coupled with built-in scrubber to maximize integrity of space systems.
  • Commercial-off-the-shelf (COTS) plastic components speed up prototype build and maintain same design for flight.
  • Low latency, deterministic instant-on combined with superior size, weight, and power specifications to ensure successful missions.

Solving Satellite Systems Architectural Bottlenecks

For more information about qualified, flight-tested FPGAs contact CAES.

Jump to

Example Applications

Sensor Control

  • Bridge processor to sensors for distributed architectures
  • Small packages and soft RISC-V Cores for control / management
  • Embedded ADC and DAC blocks to simplify design and test

Telemetry

  • Instant-on performance enable fast response and boot time requirements
  • In-orbit reconfiguration to future proof your design
  • Large on-chip memory for on-chip processing and storage

Data Acquisition

  • Digital Signal Processing to offload SBC and accelerate complex functions
  • High speed Serdes simplifies design and supports multiple protocols
  • Vision interface and signal processing adapts to a variety of sensors

Reference Designs

Object Classification Reference Design

Reference Design

Object Classification Reference Design

A reference design for implementing object classification based on Mobilenet NN model running on Lattice CertusPro-NX low power FPGA
Object Classification Reference Design
Sensor Interfacing and Preprocessing

Reference Design

Sensor Interfacing and Preprocessing

Aggregates data from multiple I2C interfaces and performs preprocessing like buffering, timestamping and complex event triggering based on data analysis.
Sensor Interfacing and Preprocessing
SPI Slave to PWM Generation

Reference Design

SPI Slave to PWM Generation

Sets the frequency and duty cycle of a PWM (Pulse-Width Modulator) using data from an external SPI master.
SPI Slave to PWM Generation
ADC Interface

Reference Design

ADC Interface

Interfaces with the Texas Instruments (TI) ADS64XX family of ADCs via LatticeECP3 FPGA high-speed LVDS I/O
ADC Interface
ECC Module Reference Design

Reference Design

ECC Module Reference Design

Provides Single Error Correction - Double Error Detection (SECDED) capability based on a class of optimal minimum oddweight error parity codes
ECC Module Reference Design

Demos

Object Classification Demonstration

Demo

Object Classification Demonstration

Sample demonstration for object detection, classification, and tracking multiple objects running on a low power general purpose FPGA using CNN Model
Object Classification Demonstration
Lattice Image Signal Processing Demo

Demo

Lattice Image Signal Processing Demo

Provides a complete ISP example design on the Lattice ECP5 FPGA for the Embedded Vision Development Kit, ideal for Industrial, Medical, and Automotive applications.
Lattice Image Signal Processing Demo

IP Cores

UART 16550 IP Core

IP Core

UART 16550 IP Core

Configurable UART port. Compatible with PC16550D. 7 or 8 bit data width, 1, 1.5, 2 stop bits for Tx. Multiple parity and baud rate options.
UART 16550 IP Core

Development Kits & Boards

CertusPro-NX Voice and Vision Machine Learning Board

Board

CertusPro-NX Voice and Vision Machine Learning Board

Design AI use cases for the Edge quickly! This board along with the Lattice sensAI solution stack provide the tools for developing vision and audio-based AI applications.
CertusPro-NX Voice and Vision Machine Learning Board

Documention

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices
FPGA-TN-02257 1.1 5/31/2022 PDF 1 MB
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 1.6 10/31/2022 PDF 1 MB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 1.4 6/9/2022 PDF 1.3 MB
Reflow Temperature Guidelines and Moisture Sensitivity
FPGA-TN-02041 4.6 8/31/2022 PDF 467.8 KB
Thermal Management
FPGA-TN-02044 4.3 9/26/2022 PDF 912.1 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices
FPGA-TN-02257 1.1 5/31/2022 PDF 1 MB
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 1.6 10/31/2022 PDF 1 MB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 1.4 6/9/2022 PDF 1.3 MB
Reflow Temperature Guidelines and Moisture Sensitivity
FPGA-TN-02041 4.6 8/31/2022 PDF 467.8 KB
Thermal Management
FPGA-TN-02044 4.3 9/26/2022 PDF 912.1 KB
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