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  • AHB2AHB IP Core

    IP Core

    AHB2AHB IP Core

    The uni-directional AHB/AHB bridge is used to connect two AMBA AHB 2.0 buses clocked by synchronous clocks with any frequency ratio. The bridge is connected through a pair consisting of an AHB slave and an AHB master interface.
    AHB2AHB IP Core
  • AHB2AXIB IP Core

    IP Core

    AHB2AXIB IP Core

    This bridge allows to access an AXI3 or AXI4 slave from an AHB bus through an AHB 2.0 slave interface. The bridge has an AHB slave interface on the AHB side and AXI3 or AXI4 master interface on the AXI side.
    AHB2AXIB IP Core
  • FTMCTRL - Combined PROM/IO/SRAM/SDRAM Memory controller with EDAC IP Core

    IP Core

    FTMCTRL - Combined PROM/IO/SRAM/SDRAM Memory controller with EDAC IP Core

    Combined PROM/IO/SRAM/SDRAM Memory controller with optional EDAC. The PROM, SRAM and SDRAM areas can be EDAC-protected using a (39, 7) BCH code. The EDAC provides single error correction and double-error detection for each 32-bit memory word.
    FTMCTRL - Combined PROM/IO/SRAM/SDRAM Memory controller with EDAC IP Core
  • GR1553B Mil-Std-1553B/AS15531 Interface IP Core

    IP Core

    GR1553B Mil-Std-1553B/AS15531 Interface IP Core

    The GR1553B core implements the MIL-STD-1553B (Notice 2) data bus protocol, with ability to serve as Bus Controller (BC), Remote Terminal (RT) or Bus Monitor (BM). The core is connected to the MIL-STD-1553B bus via a dual transceiver interface
    GR1553B Mil-Std-1553B/AS15531 Interface IP Core
  • GRCAN - CAN 2.0B Controller IP Core

    IP Core

    GRCAN - CAN 2.0B Controller IP Core

    The GRCAN core is a CAN controller with an AHB DMA backend. The APB bus is used for configuration, control and status handling and the AHB bus is used for retrieving and storing CAN messages in memory external to the CAN controller.
    CAN, AHB, DMA 
    GRCAN - CAN 2.0B Controller IP Core
  • GRETH - 10/100 Ethernet MAC IP Core

    IP Core

    GRETH - 10/100 Ethernet MAC IP Core

    The GRETH core implements a 10/100 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface. The core implements the 802.3-2002 Ethernet standard.
    GRETH - 10/100 Ethernet MAC IP Core
  • GRETH_GBIT 10/100/1000 Ethernet MAC IP Core

    IP Core

    GRETH_GBIT 10/100/1000 Ethernet MAC IP Core

    The GRETH_GBIT core implements a 10/100/1000 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface. The core implements the 802.3-2002 Ethernet standard.
    GRETH_GBIT 10/100/1000 Ethernet MAC IP Core
  • GRHSSL - High Speed Serial Link Controller IP Core

    IP Core

    GRHSSL - High Speed Serial Link Controller IP Core

    The GRHSSL IP is a highly configurable high-speed serial link controller, described in VHDL. It can implement a SpaceFibre controller, a WizardLink controller or both.
    GRHSSL - High Speed Serial Link Controller IP Core
  • GRPCI IP Core

    IP Core

    GRPCI IP Core

    The GRPCI IP core provides a 32-bit master/target interface for AMBA AHB 2.0 systems. It includes parameterizable FIFOs for both master and target operation and can optionally be provided with an independent DMA engine.
    GRPCI IP Core
  • GRSPW_CODEC SpaceWire Codec IP Core

    IP Core

    GRSPW_CODEC SpaceWire Codec IP Core

    The GRSPW_CODEC core implements a SpaceWire encoder decoder with a 9-bit wide FIFO host interface in each direction. The core complies to the SpaceWire standard (ECSS-E-ST-12C). Data is transmitted and received through FIFOs with configurable depth.
    GRSPW_CODEC SpaceWire Codec IP Core
  • GRSPW2 SpaceWire Link IP Core

    IP Core

    GRSPW2 SpaceWire Link IP Core

    The GRSPW2 implements a SpaceWire link controller with RMAP support and AMBA host interface. The core complies to the SpaceWire standard (ECSS-E-ST-50-12C) with the protocol identification extension (ECSS-E-ST-50-51C) and RMAP protocol (ECSS-E-ST-50-52C).
    GRSPW2 SpaceWire Link IP Core
  • GRSPWROUTER SpaceWire Routing Switch IP Core

    IP Core

    GRSPWROUTER SpaceWire Routing Switch IP Core

    The GRSPWROUTER is a VHDL model of a SpaceWire routing switch. The core is highly configurable, flexible and it supports all mandatory and optional features in the ECSS-E-ST-50-12C standard.
    GRSPWROUTER SpaceWire Routing Switch IP Core
  • GRUSBDC - USB 2.0 Device Controller IP Core

    IP Core

    GRUSBDC - USB 2.0 Device Controller IP Core

    GRUSBDC provides an interface between an USB 2.0 bus and an AMBA-AHB 2.0 bus. The core is used for implementing USB 2.0 functions providing access to the USB through either an AHB slave or an AHB master interface.
    GRUSBDC - USB 2.0 Device Controller IP Core
  • GRUSBHC - USB 2.0 Host Controller IP Core

    IP Core

    GRUSBHC - USB 2.0 Host Controller IP Core

    The USB 2.0 Host Controller provides a link between the AMBA on-chip bus and the Universal Serial Bus (USB). The host controller supports High-, Full- and Low-Speed USB traffic. The core can handle up to 15 downstream ports, where each port can handle all three USB speeds.
    GRUSBHC - USB 2.0 Host Controller IP Core
  • L2C IP Core

    IP Core

    L2C IP Core

    The L2C (Level 2 Cache controller) implements a Level-2 cache for processors with AHB interfaces. The L2C works as an AHB to AHB/AXI bridge, caching data that is read or written via the bridge.
    L2C IP Core
  • LEON3 Processor IP Core

    IP Core

    LEON3 Processor IP Core

    The LEON3 is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable and particularly suitable for system-on-a-chip (SOC) designs.
    LEON3 Processor IP Core
  • NAND Flash Memory Controller with DMA IP Core

    IP Core

    NAND Flash Memory Controller with DMA IP Core

    NANDFCTRL2 is a VHDL IP core implementing a memory controller for NAND flash memory devices and is designed to operate with ONFI 4.0 flash memory devices.
    NAND Flash Memory Controller with DMA IP Core
  • NOEL-V RISC-V Processor IP Core

    IP Core

    NOEL-V RISC-V Processor IP Core

    The NOEL-V is a VHDL model of a processor that implements the RISC-V architecture, which can be configured to conform to the RV32 or RV64 architectures.
    NOEL-V RISC-V Processor IP Core
  • SPIMCTRL - SPI Memory Controller IP Core

    IP Core

    SPIMCTRL - SPI Memory Controller IP Core

    This SPI memory controller maps a memory device connected via the Serial Peripheral Interface (SPI) into AMBA address space. Read accesses are performed by performing normal AMBA read operations in the mapped memory area.
    SPIMCTRL - SPI Memory Controller IP Core
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