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  • RISC-V RX and LPDDR4 Memory Controller Reference Design

    Reference Design

    RISC-V RX and LPDDR4 Memory Controller Reference Design

    RISC-V RX & LPDDR4 Memory Controller Reference Design shows usage of the RISC-V RX soft IP & LPDDR4 memory controller in Lattice Avantâ„¢ & CertusProâ„¢ NX.
    RISC-V RX and LPDDR4 Memory Controller Reference Design
  • ULX3S by Radiona.org

    Board

    ULX3S by Radiona.org

    A fully open source, compact, robust, and affordable ECP5 FPGA dev board equipped with a balanced selection of additional components and expansions.
    ULX3S by Radiona.org
  • AK-MACHXO2-7000 Development Board

    Board

    AK-MACHXO2-7000 Development Board

    Low-cost development platform featuring the MachXO2-7000 FPGA, Ethernet, SDRAM, microSD, serial flash, UART, VGA output and an embedded JTAG programmer
    AK-MACHXO2-7000 Development Board
  • FTMCTRL - Combined PROM/IO/SRAM/SDRAM Memory controller with EDAC IP Core

    IP Core

    FTMCTRL - Combined PROM/IO/SRAM/SDRAM Memory controller with EDAC IP Core

    Combined PROM/IO/SRAM/SDRAM Memory controller with optional EDAC. The PROM, SRAM and SDRAM areas can be EDAC-protected using a (39, 7) BCH code. The EDAC provides single error correction and double-error detection for each 32-bit memory word.
    FTMCTRL - Combined PROM/IO/SRAM/SDRAM Memory controller with EDAC IP Core
  • Standard SDRAM Controller for ispMACH Devices

    Reference Design

    Standard SDRAM Controller for ispMACH Devices

    SDRAM Interface to standard microprocessors, independent of the processor type. The design as shown supports two 16MB memory regions configured as 4 M x 32 bits
    Standard SDRAM Controller for ispMACH Devices
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