• 莱迪思解决方案

莱迪思解决方案

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  • RISC-V RX and LPDDR4 Memory Controller Reference Design

    Reference Design

    RISC-V RX and LPDDR4 Memory Controller Reference Design

    RISC-V RX & LPDDR4 Memory Controller Reference Design shows usage of the RISC-V RX soft IP & LPDDR4 memory controller in Lattice Avant™ & CertusPro™ NX.
    Avant-E, CertusPro-NX 
    RISC-V, LPDDR4, AXI4, SDRAM, IEEE 1149.1, Lattice Propel 
    RISC-V RX and LPDDR4 Memory Controller Reference Design
  • ULX3S by Radiona.org

    Board

    ULX3S by Radiona.org

    A fully open source, compact, robust, and affordable ECP5 FPGA dev board equipped with a balanced selection of additional components and expansions.
    ECP5 / ECP5-5G 
    第三方资源, Battery, Bluetooth-BLE, WiFi, ADC/DAC, SD Memory, SDRAM 
    ULX3S by Radiona.org
  • AK-MACHXO2-7000开发板

    Board

    AK-MACHXO2-7000开发板

    ARTEKIT XO2开发板
    MachXO2  
    Ethernet, RS-232, SD Memory, SDRAM, VGA 
    AK-MACHXO2-7000开发板
  • FTMCTRL - Combined PROM/IO/SRAM/SDRAM Memory controller with EDAC IP Core

    IP Core

    FTMCTRL - Combined PROM/IO/SRAM/SDRAM Memory controller with EDAC IP Core

    Combined PROM/IO/SRAM/SDRAM Memory controller with optional EDAC. The PROM, SRAM and SDRAM areas can be EDAC-protected using a (39, 7) BCH code. The EDAC provides single error correction and double-error detection for each 32-bit memory word.
    CertusPro-NX, CrossLink-NX, Certus-NX 
    SDRAM, AHB 
    FTMCTRL - Combined PROM/IO/SRAM/SDRAM Memory controller with EDAC IP Core
  • 针对ispMACH器件的标准SDRAM控制器

    Reference Design

    针对ispMACH器件的标准SDRAM控制器

    SDRAM Interface to standard microprocessors, independent of the processor type. The design as shown supports two 16MB memory regions configured as 4 M x 32 bits
    ispMACH 4000ZE, ispMACH 4000V/B/C/Z 
    SDRAM 
    针对ispMACH器件的标准SDRAM控制器
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