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  • PCIe Basic Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Basic Demo for Lattice Nexus-based FPGAs

    The PCIe Basic Demo allows you to control three 7 segment LEDs and manipulate the onboard memory of the FPGA through the PCIe slot.
    PCIe Basic Demo for Lattice Nexus-based FPGAs
  • PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    PCIe Colorbar Demo displays a series of moving colorbars by streaming the image data using DMA transfers from the FPGA to the host system.
    PCIe Colorbar Demo for Lattice Nexus-based FPGAs
  • PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    The PCI Express DMA Throughput Demo allows to initiate DMA read and write transactions, transferring data from the host to the FPGA and vice versa.
    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs
  • PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demonstrates the multifunction capabilities of the Crosslink-NX FPGA that allows access to GPIO, MDIO and I2C registers.
    PCIe Multifunction Demo for Lattice Nexus-based FPGAs
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
    RISC-V MC CPU IP Core
  • RISC-V RX CPU IP Core

    IP Core

    RISC-V RX CPU IP Core

    Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.
    RISC-V RX CPU IP Core
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • Tightly-Coupled Memory (TCM) IP Core

    IP Core

    Tightly-Coupled Memory (TCM) IP Core

    The Tightly-Coupled Memory IP ensures low-latency automatic selection of the best memory type for user-selected application.
    Tightly-Coupled Memory (TCM) IP Core
  • DDR3 Memory Interface Demonstration

    Demo

    DDR3 Memory Interface Demonstration

    The Lattice DDR3 Memory Interface demonstrates the functionality of DDR3 SDRAM Controller IP at core speed of 400MHz and 800Mbps.
    DDR3 Memory Interface Demonstration
  • Certus-NX Versa Evaluation Board

    Board

    Certus-NX Versa Evaluation Board

    The Certus-NX Versa Evaluation Board enables designers with connectivity features of the Certus-NX FPGA and assist engineers with prototyping and testing.
    Certus-NX Versa Evaluation Board
  • Image Signal Processing IP Cores Suite

    IP Core

    Image Signal Processing IP Cores Suite

    The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.
    Image Signal Processing IP Cores Suite
  • PCI Express for Nexus FPGAs

    IP Core

    PCI Express for Nexus FPGAs

    The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express for Nexus FPGAs
  • Video Scaler IP Core

    IP Core

    Video Scaler IP Core

    The Lattice Video Scaler IP Core is used to scale up or scale down the resolution of a video stream.
    Video Scaler IP Core
  • FreeRTOS

    IP Core

    FreeRTOS

    FreeRTOS software included in Lattice Propel 2022.1 for RISC-V embedded processor available with real-time kernel and set of libraries.
  • CNN Plus Accelerator IP Core

    IP Core

    CNN Plus Accelerator IP Core

    CNN Plus IP is a flexible accelerator IP that simplifies implementation of Ultra-Low power AI by leveraging capabilities of Lattice FPGAs.
    CNN Plus Accelerator IP Core
  • CSI-2/DSI D-PHY Transmitter IP Core

    IP Core

    CSI-2/DSI D-PHY Transmitter IP Core

    The CSI-2/DSI D-PHY Transmitter Submodule IP is for applications requiring D-PHY transmitter in the FPGA logic & supports both high-speed & low power modes
    CSI-2/DSI D-PHY Transmitter IP Core
  • FPD-LINK Receiver

    IP Core

    FPD-LINK Receiver

    Modular MIPI/D-PHY IP - Converts FPD-LINK Video Streams to Pixel Clock Domain
    FPD-LINK Receiver
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