The Lattice Semiconductor Unified Interconnect IP Core delivers an advanced, low-latency interconnect fabric optimized for APB, AHB-Lite, AXI4 and AXI4-Lite systems. Designed for efficiency and scalability, it enables seamless migration for designs that meet the feature requirements.
Resource Utilization details are available in the IP Core User Guide.
Features
- Each external manager (EM) or external subordinate (ES) can be configured to support various protocols.
- AMBA 4 AXI4
- AMBA 4 AXI4-Lite
- AMBA 3 AHB-Lite
- AMBA 3 APB
- Configurable interface data widths:
- AXI4: 8, 16, 32, 64, 128, 256, 512, or 1,024 bits
- AXI4-Lite: 32 or 64 bits
- AHB-Lite: 8, 16, 32, 64, 128, 256, 512, or 1,024 bits
- APB: 8, 16, or 32 bits
- Address widths:
- AXI4: Up to 64 bits (11 to 64)
- AXI4-Lite: Up to 64 bits (11 to 64)
- AHB-Lite: Up to 32 bits (11 to 32)
- APB: Up to 32 bits (11 to 32)
- Supports AXI4 with the following characteristics:
- User width: Up to 128 bits
- ID width: Up to 6 bits
- INCR and FIXED bursts.
- Supports three types of responses:
- AXI OKAY
- AXI DECERR – when undefined external subordinate address region is accessed.
- AXI SLVERR – for pass through from the external subordinate.
- Supports three types of responses:
- Supports reduced resource optimization, including:
- Read-only manager and subordinate
- Write-only manager and subordinate
- Crossbar paths restriction with configured connectivity map
