Unified Interconnect IP Core

High-performance and Low-latency Interconnect Fabric

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The Lattice Semiconductor Unified Interconnect IP Core delivers an advanced, low-latency interconnect fabric optimized for AXI4 and AXI4-Lite systems, achieving up to 60% reduction in resource utilization compared to current AXI4 Interconnect IP with the similar configuration.

This IP core allows any AXI4- or AXI4-Lite-compliant component to integrate effortlessly within your system architecture, connecting one or more memory-mapped manager devices to multiple subordinate devices. For designs requiring multi-clock environments, optional Clock Domain Crossing (CDC) is supported. Review the feature comparison table below to determine migration suitability and unlock the benefits of Unified Interconnect.

Resource Utilization details are available in the IP Core User Guide

Features

  • 60% reduction in resource utilization compared to current AXI4 interconnect with similar configuration (4EMs x 4ESs).
  • Configurable interface data widths:
    • AXI4: 8,16 32, 64, 128, 256, 512, or 1,024 bits
    • AXI4-Lite: 32 or 64 bits
  • Address widths:
    • AXI4: Up to 64-bits (13 to 64)
    • AXI4-Lite: Up to 64-bits (13 to 64)
  • Supports AXI4 with the following characteristics:
    • User width: Up to 128 bits
    • ID width: Up to 6 bits
    • INCR and FIXED bursts.

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Block Diagram

Unified Interconnect - GraphicsExpand Image

Unified Interconnect - Block Diagram

Table

Unified Interconnect vs AXI4 Interconnect IP Comparison with Migration Guide
Parameter Unified Interconnect IP AXI4 Interconnect IP Migration Guide
Max External Managers 1–4 Up to 32 managers Reduce manager count to ≤4; consolidate
initiators or use hierarchy.
Max External Subordinates 1–4 Up to 32 subordinates Limit subordinate count to ≤4;
group peripherals
under shared address regions.
AXI User Width 1–128 1–128 Verify user signal mapping.
Memory Type of Large FIFO LUT, EBR LUT, EBR No change required; both support
LUT and EBR.
Crossbar Optimization Strategy Maximize Performance or Minimize Area
(only if all ports AXI4-Lite)		 Configuration not available for user Minimize Area option only available when
all ports are AXI4-Lite.
Protocol Support AXI4, AXI4-Lite AXI4, AXI4-Lite No change required; both support
AXI4 and AXI4-Lite.
Data Width Options AXI4: 8–1024 bits; AXI4-Lite: 32 or 64 bits
(No DWC; EM and ES must share
the same data width)		 AXI4: 8–1024 bits;
AXI4-Lite: 32 or 64 bits
(Supports Data Width Conversion)		 Match widths; ensure AXI4-Lite ports use
only 32 or 64 bits.
Address Width 13–64 bits 13–64 bits No change required; same range
supported.
AXI ID Width EM: 1–6; ES: 1–8 EM: 1–6; ES: 1–11 Reduce ID width if larger than 6 for
EM or 8 for ES.
CDC Enable Per-port: Checked/Unchecked Per-port: Checked/Unchecked No change required; same capability.
Acceptance Limits 1–32 per EM 2–16 per EM The Unified Interconnect supports a higher
acceptance limit for read and
write transactions exclusively.
Issuance Limits No limit setting available 2–16 per EM The issuance limit for each ES port is computed
based on the sum of the total acceptance
limits of all associated EM ports.
Fragmented Address Space Up to 16 fragments per ES Up to 16 fragments per ES No change required; same capability.
Arbitration Scheme Round Robin or Fixed Priority,
applicable only to EM ports
setting		 Round Robin or Fixed Priority,
applicable to EM and ES ports
setting independently		 Both support same schemes; the
ES port arbitration scheme has been
removed. Please adjust priorities
based on the EM port settings.
Per Port Data Buffering Data channels up to 512-entry
depth; Address and response
channels up to 16 entries depth;
supports zero buffering		 Data channel up to 512 entries
depth; Response channels up to
16 entries depth; no address
channels setting; minimum buffer
depth restricted to 2		 No change required; user may
configure address channels
buffer depth to benefit.

Ordering Information

The Unified Interconnect IP is provided at no additional cost with the Lattice Radiant software and Lattice Propel design environment.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Unified Interconnect IP User Guide
FPGA-IPUG-02318 1.0 12/11/2025 PDF 1.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Unified Interconnect IP Release Notes
FPGA-RN-02107 1.0 12/11/2025 PDF 236.3 KB

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