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  • Lattice Sentry PLD Interface IP Core

    IP Core

    Lattice Sentry PLD Interface IP Core

    Lattice Semiconductor Customer Programmable Logic Devices (PLD)implements a bidirectional mailbox for sending and receiving messages.
    Lattice Sentry PLD Interface IP Core
  • Timer/Counter IP Core

    IP Core

    Timer/Counter IP Core

    Timer/Counter IP used to track timeouts in the system. Target devices are Certus-NX and Crosslink-NX.
    Timer/Counter IP Core
  • Lattice Sentry ESB Mux IP Core for MachXO3D

    IP Core

    Lattice Sentry ESB Mux IP Core for MachXO3D

    Propel IP Module for Lattice Sentry: Enables access the MachXO3D embedded security block (ESB) simultaneously with internal crytographic operations
    Lattice Sentry ESB Mux IP Core for MachXO3D
  • Lattice Sentry I2C Monitor IP Core for MachXO3D

    IP Core

    Lattice Sentry I2C Monitor IP Core for MachXO3D

    Propel IP Module for Lattice Sentry: Monitors traffic on I2C bus to identify and block potentially illegal traffic.
    Lattice Sentry I2C Monitor IP Core for MachXO3D
  • Lattice Sentry QSPI Monitor IP Core for MachXO3D

    IP Core

    Lattice Sentry QSPI Monitor IP Core for MachXO3D

    Propel IP Module for Lattice Sentry: Monitors traffic on SPI/QSPI bus to identify and block potentially illegal traffic.
    Lattice Sentry QSPI Monitor IP Core for MachXO3D
  • Lattice Sentry QSPI Streamer IP Core for MachXO3D

    IP Core

    Lattice Sentry QSPI Streamer IP Core for MachXO3D

    Propel IP Module for Lattice Sentry: Provides fast SPI memory access for firmware authentication as part fo Platform Root of Trust operation
    Lattice Sentry QSPI Streamer IP Core for MachXO3D
  • PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    IP Core

    PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express x1 & x4 IP Core for Nexus-based FPGAs
  • DC-SCM LVDS Tunneling Protocol and Interface IP Core

    IP Core

    DC-SCM LVDS Tunneling Protocol and Interface IP Core

    LTPI IP Core is an Open Computer Project Data Center – Secure Control Module Standards compatible solution which is introduced in the DC-SCM 2.0 Specification.
    DC-SCM LVDS Tunneling Protocol and Interface IP Core
  • LVDS Tunneling Protocol and Interface Reference Design

    Reference Design

    LVDS Tunneling Protocol and Interface Reference Design

    The DC-SCM 2.0 LTPI Reference Design provides multiple solution compliant with DC-SCM 2.0 with a standardized DC-SCI and aggregating multiple data channels.
    LVDS Tunneling Protocol and Interface Reference Design
  • 10Gb Ethernet PCS IP Core

    IP Core

    10Gb Ethernet PCS IP Core

    The 10Gb Ethernet PCS IP Core provides XGMII interface to MAC and follows IEEE802.3 10G Base-R standard.
    10Gb Ethernet PCS IP Core
  • Memory Controller IP Core

    IP Core

    Memory Controller IP Core

    The Lattice Semiconductor Memory Controller Interface module provides a solution to interface to LPDDR4 DDR memory standards.
    Memory Controller IP Core
  • SLVS-EC Receiver IP Core

    IP Core

    SLVS-EC Receiver IP Core

    The SLVS-EC RX IP provides the FPGA an interface to receive serial data from CMOS Image Sensors and offers a solution to convert the incoming serial data to a parallel pixel data format.
    SLVS-EC Receiver IP Core
  • SPI Flash Memory Controller IP Core

    IP Core

    SPI Flash Memory Controller IP Core

    The Serial Peripheral Interface (SPI) flash memory controller provides an industry-standard interface between a central processing unit (CPU) and an off-chip SPI flash memory device.
    SPI Flash Memory Controller IP Core
  • AHB-Lite to APB Bridge Module

    IP Core

    AHB-Lite to APB Bridge Module

    Propel IP Module: Bridges high-speed AHB-lite to low-power APB. Data bus widths up to 32 bits. Address width up to 32 bits.
    AHB-Lite to APB Bridge Module
  • APB Interconnect Module

    IP Core

    APB Interconnect Module

    Propel IP Module: Fully parameterized to connect up to 32 APB bus masters and 32 slaves. Data bus width up to 32 bits. Address width up to 32 bits.
    APB Interconnect Module
  • EFB Module

    IP Core

    EFB Module

    Propel IP Module: Implements the Embedded Function Block (EFB) in MachXO3D, including I2C, Configuration Blocks and User Flash Memory with an APB Interface.
    EFB Module
  • UART IP Core

    IP Core

    UART IP Core

    Propel IP Module: Similar to NS16450 UART for serial communication supporting RS-232.
    UART IP Core
  • GPIO IP Core

    IP Core

    GPIO IP Core

    Detects and controls GPIOs via Lattice Memory Mapped Interface (LMMI) or Advanced Peripheral Bus Interface (APB).
    GPIO IP Core
  • SPI Master IP Core

    IP Core

    SPI Master IP Core

    Communicates with external SPI slave devices. Configurable data width, FIFO Tx/Rx depth, polarity, clocking modes and memory interface.
    SPI Master IP Core
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