LVDS Tunneling Protocol and Interface Reference Design

Multiple Solution Compliant with DC-SCM and Aggregate Multiple Data Channel

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The DC-SCM 2.0 LTPI Reference Design provides multiple solution templates that uses the current LVDS Tunneling Protocol Interface (LTPI) IP that is compliant with Datacenter-ready Secure Control Module (DC-SCM) 2.0 LTPI specifications with a standardized Datacenter-ready Secure Control Interface (DC-SCI), aggregating multiple data channels such as I2C, GPIO, and UART to add more flexibility to a customer’s system and board design.

DC-SCM is a sub-project of the OCP Hardware Management Project. DC-SCM implements modular server management that contains all the FW states previously housed on a typical processor motherboard. DC-SCM moves three key elements to a common form factor module which are Management (Typical BMC functions plus LTPI), Security, and Control.

One of the significant changes in the DC-SCM 2.0 specification is the introduction of Low-voltage differential signaling Tunneling Protocol & Interface (LTPI). The LTPI addresses shortcomings of the Serial GPIO interface used in DC-SCM 1.0.

Multiple interfaces tunneling - LTPI interface is designed for tunneling various low-speed signals between the HPM and SCM. It allows for tunneling of not only GPIOs but also low-speed serial interfaces such as SMBus, I2C, UART. It is also extensible with additional proprietary OEM interfaces and provides support for raw Data tunneling between HPM CPLD and SCM CPLD.

High bandwidth capabilities - The LVDS interface provides higher bandwidth up to 800 Mbps LVDS data rate and better scalability than the SGPIO interface introduced in DC-SCM 1.0.


  • Compliant with DC-SCM Protocol Specifications 2.0 (LTPI version 0.9)
  • Supports Link initialization, discovery, and negotiation
  • Supports Multi-channel Serial Interface and LVDS
  • Supports up to five channels aggregation/disaggregation in total
  • Supports AMBA 3 APB Protocol version 1.0 for register access of the soft IP and data channel

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Block Diagram

LVDS Tunneling Protocol and Interface Reference Design Block Diagram

Resource Utilization

  Design 1 Added Channels (MachXO3D)
Module SCM HPM Base Configuration (8-bit LL I/O only) +1 8-bit LL I/O +1 8-bit NL I/O +1 Controller I2C +1 Target I2C +1 UART
LUT4 1362 1405 974 0 2 157 96 16
PFU Registers 1137 1129 843 8 15 128 68 19
Slice 858 853 - - - - - -
I/O 39 39 - - - - - -


Technical Resources
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LVDS Tunneling Protocol and Interface Reference Design - Source Code
8/12/2022 ZIP 29.4 MB
LVDS Tunneling Protocol and Interface Reference Design - User Guide
FPGA-RD-02247 1.1 12/27/2022 PDF 2.2 MB

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