Lattice Solutions

Everything you need to quickly and easily complete your design

Share This Result >

Narrow Your Results



Solution Type



Device Support






















Tags


































































Providers

Clear All
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • iCE40 Ultra Breakout Board

    Board

    iCE40 Ultra Breakout Board

    A simple, low-cost board with rich IO access for evaluation and development with the iCE40 Ultra FPGA.
    iCE40 Ultra Breakout Board
  • Infrared Remote Tx/Rx Reference Designs

    Reference Design

    Infrared Remote Tx/Rx Reference Designs

    Implements an interface to IR receive and/or IR transmit. This includes PWM (pulse width modulation) timing and protocol conversion to an SPI /I2C bus
    Infrared Remote Tx/Rx Reference Designs
  • RGB LED Reference Design

    Reference Design

    RGB LED Reference Design

    A complete RGB LED design that controls the color, blinking rate, brightness and breathing of an RGB LED.
    RGB LED Reference Design
  • ​​I3C-SC: MIPI I3C Basic Secondary Controller​

    IP Core

    ​​I3C-SC: MIPI I3C Basic Secondary Controller​

    ​​Highly featured I3C Basic Secondary Controller (Controller-Capable Slave). Optional I3C-to-AHB bridge functionality from over-I3C remote access of local AHB bus. Works to any Lattice FPGA device.​
    ​​I3C-SC: MIPI I3C Basic Secondary Controller​
  • ​​I3C-T - MIPI I3C Basic Target​

    IP Core

    ​​I3C-T - MIPI I3C Basic Target​

    ​Highly featured, SDR-Capable and HDR-Tolerant Target controller. Supports hot-join, in-band interrupts, & dynamic addressing. Works to any Lattice FPGA device​.
    ​​I3C-T - MIPI I3C Basic Target​
  • JPEG-DX-F - Ultra-Fast Baseline and Extended JPEG Decoder

    IP Core

    JPEG-DX-F - Ultra-Fast Baseline and Extended JPEG Decoder

    Scalable, ultra-high throughput 8/12-bit JPEG decoder. Ideal for low-latency motion-Jpeg streaming. Full-HD or Ultra-HD capable depending on the device.
    JPEG-DX-F - Ultra-Fast Baseline and Extended JPEG Decoder
  • JPEG-DX-S - Baseline and Extended JPEG Decoder

    IP Core

    JPEG-DX-S - Baseline and Extended JPEG Decoder

    Compact, 8bit and 12bit per color, JPEG decoder. Ideal for low-latency motion-Jpeg streaming.
    JPEG-DX-S - Baseline and Extended JPEG Decoder
  • JPEG-EX-F - Ultra-Fast Baseline and Extended JPEG Encoder

    IP Core

    JPEG-EX-F - Ultra-Fast Baseline and Extended JPEG Encoder

    Scalable, ultra-high throughput 8/12-bit encoder. Highly configurable with advanced bit-rate control. Ideal for low-latency motion-Jpeg streaming.
    JPEG-EX-F - Ultra-Fast Baseline and Extended JPEG Encoder
  • JPEG-EX-S - Baseline and Extended JPEG Encoder

    IP Core

    JPEG-EX-S - Baseline and Extended JPEG Encoder

    Compact, 8bit and 12bit per color, JPEG encoder. Highly configurable with advanced bit-rate control features. Ideal for low-latency motion-Jpeg streaming.
    JPEG-EX-S - Baseline and Extended JPEG Encoder
  • SPMI-CTRL - MIPI SPMI Master or Slave Controller

    IP Core

    SPMI-CTRL - MIPI SPMI Master or Slave Controller

    Highly featured, easy-to-use master or slave controller supporting the latest version of the MIPI-SPMI specification. Portable to any Lattice FPGA device
    SPMI-CTRL - MIPI SPMI Master or Slave Controller
  • TSN-EP – TSN Ethernet Endpoint Controller

    IP Core

    TSN-EP – TSN Ethernet Endpoint Controller

    Highly flexible core supports timing synchronization (IEEE 802.1AS), traffic shaping (IEEE 802.1Qav, Qbv) and frame-preemption (IEEE 802.1Qbu, & 802.3br).
    TSN-EP – TSN Ethernet Endpoint Controller
  • UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack

    IP Core

    UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack

    Standalone, processor-less operation with up to 32 Rx and 32 Tx channels. Supports DHCP, IGMP, ICMP, ARP with cache, Jumbo and super Jumbo IPv4 frames.
    UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack
  • Sensor Interfacing and Preprocessing

    Reference Design

  • iCE40 UltraLite Breakout Board

    Board

    iCE40 UltraLite Breakout Board

    A simple, low-cost board for evaluation and development with the iCE40 UltraLite FPGA. Includes high-power RGB LED.
    iCE40 UltraLite Breakout Board
  • LIN - LIN Bus Master/Slave Controller

    IP Core

    LIN - LIN Bus Master/Slave Controller

    Production-proven core suitable for LIN 2.2 or earlier networks. Standard and Safety Enhanced (ISO 26262) versions. Portable to any Lattice FPGA.
    LIN - LIN Bus Master/Slave Controller
  • CAN-CTRL - CAN 2.0, CAN FD, and CAN XL Bus Controller

    IP Core

    CAN-CTRL - CAN 2.0, CAN FD, and CAN XL Bus Controller

    Highly featured and multiple times production proven IP core. Available in standard and safety-enhanced (ISO 26262) versions. Portable to any Lattice FPGA
    CAN-CTRL - CAN 2.0, CAN FD, and CAN XL Bus Controller
  • Barcode Emulation

    Reference Design

    Barcode Emulation

    Enables an ordinary LED to transmit barcode data. The LED is driven such that it transmits pulses that can be read by a checkout scanner.
    Barcode Emulation
  • Pedometer Reference Design

    Reference Design

    Pedometer Reference Design

    Implement a fully-functional pedometer in a tiny, low-power FPGA. Interfaces to standard accelerometer for data acquisition.
    Pedometer Reference Design
  • Page 1 of 2
    First Previous
    1 2
    Next Last