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  • 10 Gb Ethernet MAC & PCS Reference Design

    Reference Design

    10 Gb Ethernet MAC & PCS Reference Design

    10Gb Ethernet MAC & PCS Reference Design on CertusPro-NX with data generator and checker.
    10 Gb Ethernet MAC & PCS Reference Design
  • 2.5 Gb USXGMII Ethernet IP Core

    IP Core

    2.5 Gb USXGMII Ethernet IP Core

    USXGMII IP Core is a connection bus for MACs and PHYs and is often used in bridging applications and/or PHY implementations.
    2.5 Gb USXGMII Ethernet IP Core
  • Time Sensitive Networking (TSN) End Node

    IP Core

    Time Sensitive Networking (TSN) End Node

    The Time Sensitive Networking (TSN) End Node IP supports scheduling, priority queues, credit shaping, cyclic forwarding and preemption.
    Time Sensitive Networking (TSN) End Node
  • Time Sensitive Networking (TSN) Network Node

    IP Core

    Time Sensitive Networking (TSN) Network Node

    Time Sensitive Networking (TSN) Switched End Node IP supports 3 Ports, scheduling, priority queues, credit shaping, redundancy, cyclic forwarding and preemption
    Time Sensitive Networking (TSN) Network Node
  • TSN-EP – TSN Ethernet Endpoint Controller

    IP Core

    TSN-EP – TSN Ethernet Endpoint Controller

    Highly flexible core supports timing synchronization (IEEE 802.1AS), traffic shaping (IEEE 802.1Qav, Qbv) and frame-preemption (IEEE 802.1Qbu, & 802.3br).
    TSN-EP – TSN Ethernet Endpoint Controller
  • UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack

    IP Core

    UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack

    Standalone, processor-less operation with up to 32 Rx and 32 Tx channels. Supports DHCP, IGMP, ICMP, ARP with cache, Jumbo and super Jumbo IPv4 frames.
    UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack
  • MDIO Peripheral - WISHBONE Compatible

    Reference Design

    MDIO Peripheral - WISHBONE Compatible

    Implements an MDIO (Management Data Input/Output Interface) slave interface as specified in the IEEE 802.3 standard.
    MDIO Peripheral - WISHBONE Compatible
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