Lattice Solutions

IP Core

FFT Compiler IP Core

The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, Certus-NX, CertusPro-NX, MachXO5-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X 

Data Communication, DSP, Guidance Systems, Automotive, DSP Bundle, SDR 

IP Core

FIR Filter Generator IP Core

This IP core is a widely configurable, multi-channel FIR filter, implemented using high performance sysDSP™ blocks available in Lattice devices.

ECP5 / ECP5-5G, LatticeECP3, LatticeXP2, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E, Avant-G, Avant-X 

DSP, Guidance Systems, Automotive, DSP Bundle, SDR 

Board

Avant-E Evaluation Board

The Avant-E Evaluation Board has the ability to expand the usability of the Avant-E FPGA with FMC HPC, PMOD, and Raspberry PI connectors.

Avant-E 

Lattice Avant, SPI Flash, LPDDR4, SERDES, GPIO, PMOD, FMC, Industrial Networking, SDR, Defense 

IP Core

Image Signal Processing IP Cores Suite

The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.

CrossLink-NX, Certus-NX, CertusPro-NX, Avant-E 

AXI, AXI-Stream, AXI-Lite Interface, AWB, Camera, CCM, CFA Interpolation, Debayer, Image Processing, Image Signal Processing, Lattice mVision, RGB, Defense 

IP Core

MACsec AES256-GCM, High-speed (XIP1213H)

The high-speed MACsec IP core implements the MACsec protocol as standardized in IEEE 802.1AE-2018, defining a security infrastructure for OSI model Layer 2 traffic.

Avant-E, Avant-G, Avant-X 

AES, Encryption, NIST, Security, ECC, Public/Private Key, SHA, SDR 

IP Core

QSPI Flash Controller IP Core

The QSPI Flash Controller IP allows communication with multiple external SPI flash devices using standard, extended dual/quad, dual, or quad SPI protocols.

Avant-E, Avant-G, Avant-X, CertusPro-NX, Certus-NX 

QSPI, SPI Flash, SPI, Flash 

IP Core

ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)

ML-KEM-512/768/1024 is an IP core for post-quantum Key Encapsulation Mechanism (KEM), optimized for a good balance between speed and resource requirements.

Avant-E, Avant-G, Avant-X, CertusPro-NX, ECP5 / ECP5-5G 

Encryption, NIST, Public/Private Key, Security, SDR 

Demo

Object Classification Demonstration

This object classification demo provides a sample application for detecting, classifying, and tracking multiple objects running on CertusPro-NX FPGA.

CertusPro-NX, Avant-E 

Machine Learning/AI, Lattice sensAI, Object Detection, Object Identification, Space 

Reference Design

Object Classification Reference Design

The Object Classification reference design shows examples on implementing machine-learning based object classification to edge devices applications.

CertusPro-NX, Avant-E, CrossLink-NX 

Machine Learning/AI, Lattice sensAI, Object Detection, Object Identification, Space 

IP Core

RISC-V MC CPU IP Core

The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).

MachXO3D, Certus-NX, CrossLink-NX, Avant-E, MachXO5-NX, CertusPro-NX, MachXO3, MachXO2, Avant-G, Avant-X, ECP5 / ECP5-5G 

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive, SDR 

IP Core

RISC-V SM CPU IP Core

Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.

Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX, MachXO3D, MachXO3, MachXO2, Avant-G, Avant-X, ECP5 / ECP5-5G 

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive, SDR 

IP Core

RISC-V RX CPU IP Core

Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.

Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX, Avant-G, Avant-X, ECP5 / ECP5-5G 

AHB-Lite, Soft Processor, RISC-V, RTOS, Lattice Propel, Defense, Automotive 

IP Core

Timer/Counter IP Core

The Lattice Semiconductor Timer/Counter IP is used to track timeouts in the system, and it generates an interrupt to the CPU when a timeout is detected.

Certus-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X, CertusPro-NX, CrossLink, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 LP/HX, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP2/M, LatticeECP3, LatticeSC/M, LatticeXP2, Mach-NX, MachXO, MachXO2, MachXO3, MachXO3D, MachXO5-NX 

AMBA, Lattice Propel, Lattice Diamond, Lattice Radiant, APB, AHB-Lite, Lattice Sentry, Lattice Sentry PFR IP Package, Security 

IP Core

Tightly-Coupled Memory (TCM) IP Core

The Tightly-Coupled Memory IP ensures low-latency automatic selection of the best memory type for user-selected application.

Avant-E, Avant-G, Avant-X, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX 

Embedded Ram, FIFO, Lattice Propel, Lattice Diamond, Lattice Radiant, Defense 

IP Core

Advanced CNN Accelerator IP

Calculates full layers of Neural Network including convolution layer, pooling layer, batch normalization layer, and fully connected layer.

CertusPro-NX, Avant-E 

Machine Learning/AI, Lattice sensAI, Object Detection, Object Identification, Home Control Appliances & Security, IoT & Wearables, CNN Bundle 

IP Core

AHB-Lite to AXI4 Bridge IP Core

The Lattice AHB-Lite to AXI4 Bridge IP Core is used for interfacing one AHB-Lite Manager and one AXI4 Subordinate.

Avant-E, Avant-G, Avant-X, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX 

AHB-L, AHB-Lite, AXI4, Lattice Avant 

IP Core

AXI4 Interconnect Module

AXI4 Interconnect is a flexible, versatile, and easy-to-use IP with high-performance and low-latency interconnect fabric for AMBA 4 AXI/AXI-lite based systems.

Avant-E, Avant-G, Avant-X, CrossLink-NX, MachXO5-NX, Certus-NX, CertusPro-NX 

AMBA, AXI4, AXI, AXI-Lite Interface, Lattice Avant 

IP Core

AXI4 Multi Port Bridge for Memory Controller IP Core

The AXI4 Multi Port Bridge for Memory Controller (MPMC) IP connects multiple external managers to a single memory controller.

Avant-E, Avant-G, Avant-X, CertusPro-NX 

AXI4, Memory Controller, AXI 

Demo

MIPI CSI-2 to HDMI Demonstration

Lattice MIPI-HDMI Demonstration is built using multiple Lattice IPs and some additional glue logic necessary to connect the IPs in a processing pipeline.

Avant-E, Avant-G, Avant-X 

Lattice mVision, MIPI, HDMI, CSI-2, I2C 

Reference Design

MIPI CSI-2 to HDMI Reference Design

MIPI CSI-2 to HDMI Reference Design includes the synthesizable MIPI-HDMI core design & stimulus generators, checkers, & a testbench necessary to simulate the design

Avant-E, Avant-G, Avant-X 

Lattice mVision, MIPI, HDMI, CSI-2, I2C