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  • FFT Compiler IP Core

    IP Core

    FFT Compiler IP Core

    The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.
    FFT Compiler IP Core
  • FIR Filter Generator IP Core

    IP Core

    FIR Filter Generator IP Core

    This IP core is a widely configurable, multi-channel FIR filter, implemented using high performance sysDSP™ blocks available in Lattice devices.
    FIR Filter Generator IP Core
  • Avant-E Evaluation Board

    Board

    Avant-E Evaluation Board

    The Avant-E Evaluation Board has the ability to expand the usability of the Avant-E FPGA with FMC HPC, PMOD, and Raspberry PI connectors.
    Avant-E Evaluation Board
  • Image Signal Processing IP Cores Suite

    IP Core

    Image Signal Processing IP Cores Suite

    The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.
    Image Signal Processing IP Cores Suite
  • MACsec AES256-GCM, High-speed (XIP1213H)

    IP Core

    MACsec AES256-GCM, High-speed (XIP1213H)

    The high-speed MACsec IP core implements the MACsec protocol as standardized in IEEE 802.1AE-2018, defining a security infrastructure for OSI model Layer 2 traffic.
    MACsec AES256-GCM, High-speed (XIP1213H)
  • QSPI Flash Controller IP Core

    IP Core

    QSPI Flash Controller IP Core

    The QSPI Flash Controller IP allows communication with multiple external SPI flash devices using standard, extended dual/quad, dual, or quad SPI protocols.
  • ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)

    IP Core

    ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)

    ML-KEM-512/768/1024 is an IP core for post-quantum Key Encapsulation Mechanism (KEM), optimized for a good balance between speed and resource requirements.
    ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)
  • Object Classification Demonstration

    Demo

    Object Classification Demonstration

    This object classification demo provides a sample application for detecting, classifying, and tracking multiple objects running on CertusPro-NX FPGA.
    Object Classification Demonstration
  • Object Classification Reference Design

    Reference Design

    Object Classification Reference Design

    The Object Classification reference design shows examples on implementing machine-learning based object classification to edge devices applications.
    Object Classification Reference Design
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
    RISC-V MC CPU IP Core
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • RISC-V RX CPU IP Core

    IP Core

    RISC-V RX CPU IP Core

    Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.
    RISC-V RX CPU IP Core
  • RISC-V Nano CPU IP Core

    IP Core

    RISC-V Nano CPU IP Core

    The RISC-V Nano CPU IP contains a 32-bit RISC-V processor core that supports the RV32I instruction set and a lightweight interrupt merge controller.
    RISC-V Nano CPU IP Core
  • Tightly-Coupled Memory (TCM) IP Core

    IP Core

    Tightly-Coupled Memory (TCM) IP Core

    The Tightly-Coupled Memory (TCM) IP ensures low-latency automatic selection of the best memory type for user-selected application.
    Tightly-Coupled Memory (TCM) IP Core
  • RISC-V I/O Physical Memory Protection (IOPMP) IP Core

    IP Core

    RISC-V I/O Physical Memory Protection (IOPMP) IP Core

    RISC-V I/O Memory Protection IP protects the data in specific memory regions and allows the CPU to control external AXI manager access to AXI subordinates at run-time.
    RISC-V I/O Physical Memory Protection (IOPMP) IP Core
  • Octal SPI Controller IP Core

    IP Core

    Octal SPI Controller IP Core

    ​​Octal SPI Controller IP Core supports various types of SPI protocols & provides a flexible Transaction Layer Interface to the PCI Express Bus.​
    Octal SPI Controller IP Core
  • Driver Monitoring System (DMS) Demonstration

    Demo

    Driver Monitoring System (DMS) Demonstration

    The Driver Monitoring System Solution Demonstration highlights the capabilities of the newly introduced features of the Lattice Drive Solution Stack.
    Driver Monitoring System (DMS) Demonstration
  • AXI4 to APB Bridge Module

    IP Core

    AXI4 to APB Bridge Module

    The Lattice Semiconductor AXI4 to APB Bridge Module provides an interface between the high-speed AXI4 and APB.
    AXI4 to APB Bridge Module
  • ​​M-PESTI Initiator IP Core​

    IP Core

    ​​M-PESTI Initiator IP Core​

    ​​The Lattice M-PESTI IP core provides early peripheral presence detection and attribute collection before system boot up.​
    ​​M-PESTI Initiator IP Core​
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