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  • Avant-E Evaluation Board

    Board

    Avant-E Evaluation Board

    The Avant-E Evaluation Board has the ability to expand the usability of the Avant-E FPGA with FMC HPC, PMOD, and Raspberry PI connectors.
    Avant-E Evaluation Board
  • QSPI Flash Controller IP Core

    IP Core

    QSPI Flash Controller IP Core

    The QSPI Flash Controller IP allows communication with multiple external SPI flash devices using standard, extended dual/quad, dual, or quad SPI protocols.
  • Object Classification Demonstration

    Demo

    Object Classification Demonstration

    This object classification demo provides a sample application for detecting, classifying, and tracking multiple objects running on CertusPro-NX FPGA.
    Object Classification Demonstration
  • Object Classification Reference Design

    Reference Design

    Object Classification Reference Design

    The Object Classification reference design shows examples on implementing machine-learning based object classification to edge devices applications.
    Object Classification Reference Design
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
    RISC-V MC CPU IP Core
  • RISC-V RX CPU IP Core

    IP Core

    RISC-V RX CPU IP Core

    Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.
    RISC-V RX CPU IP Core
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • Tightly-Coupled Memory (TCM) IP Core

    IP Core

    Tightly-Coupled Memory (TCM) IP Core

    The Tightly-Coupled Memory IP ensures low-latency automatic selection of the best memory type for user-selected application.
    Tightly-Coupled Memory (TCM) IP Core
  • Advanced CNN Accelerator IP

    IP Core

    Advanced CNN Accelerator IP

    Calculates full layers of Neural Network including convolution layer, pooling layer, batch normalization layer, and fully connected layer.
    Advanced CNN Accelerator IP
  • AHB-Lite to AXI4 Bridge IP Core

    IP Core

    AHB-Lite to AXI4 Bridge IP Core

    The Lattice AHB-Lite to AXI4 Bridge IP Core is used for interfacing one AHB-Lite Manager and one AXI4 Subordinate.
    AHB-Lite to AXI4 Bridge IP Core
  • AXI4 Interconnect Module

    IP Core

    AXI4 Interconnect Module

    AXI4 Interconnect is a flexible, versatile, and easy-to-use IP with high-performance and low-latency interconnect fabric for AMBA 4 AXI/AXI-lite based systems.
    AXI4 Interconnect Module
  • AXI4 Multi Port Bridge for Memory Controller IP Core

    IP Core

    AXI4 Multi Port Bridge for Memory Controller IP Core

    The AXI4 Multi Port Bridge for Memory Controller (MPMC) IP connects multiple external managers to a single memory controller.
    AXI4 Multi Port Bridge for Memory Controller IP Core
  • Image Signal Processing IP Cores Suite

    IP Core

    Image Signal Processing IP Cores Suite

    The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.
    Image Signal Processing IP Cores Suite
  • MIPI CSI-2 to HDMI Demonstration

    Demo

    MIPI CSI-2 to HDMI Demonstration

    Lattice MIPI-HDMI Demonstration is built using multiple Lattice IPs and some additional glue logic necessary to connect the IPs in a processing pipeline.
    MIPI CSI-2 to HDMI Demonstration
  • MIPI CSI-2 to HDMI Reference Design

    Reference Design

    MIPI CSI-2 to HDMI Reference Design

    MIPI CSI-2 to HDMI Reference Design includes the synthesizable MIPI-HDMI core design & stimulus generators, checkers, & a testbench necessary to simulate the design
    MIPI CSI-2 to HDMI Reference Design
  • MPESTI Initiator Reference Design

    Reference Design

    MPESTI Initiator Reference Design

    MPESTI Initiator Reference Design provides the solution template which is compliant with the MPESTI Base Specification.
    MPESTI Initiator Reference Design
  • ​​Avant MIPI-to-Parallel and Parallel-to-MIPI Bridges Reference Design​

    Reference Design

    ​​Avant MIPI-to-Parallel and Parallel-to-MIPI Bridges Reference Design​

    ​​The design allows quick interface for a processor with a MIPI DSI with an RGB interface, or camera with MIPI CSI-2 to a processor with parallel interface​
    ​​Avant MIPI-to-Parallel and Parallel-to-MIPI Bridges Reference Design​
  • FreeRTOS

    IP Core

    FreeRTOS

    FreeRTOS software included in Lattice Propel 2022.1 for RISC-V embedded processor available with real-time kernel and set of libraries.
  • RISC-V RX and LPDDR4 Memory Controller Reference Design

    Reference Design

    RISC-V RX and LPDDR4 Memory Controller Reference Design

    RISC-V RX & LPDDR4 Memory Controller Reference Design shows usage of the RISC-V RX soft IP & LPDDR4 memory controller in Lattice Avant™ & CertusPro™ NX.
    RISC-V RX and LPDDR4 Memory Controller Reference Design
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