Timer/Counter IP Core

Configurable IP Core with 8 Timers and Automatic Interrupt Generation

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The Lattice Timer/Counter IP core can generate up to eight timers configured to operate individually. It consists of a prescaler block that counts the clock source and provides outputs divided by 2, 4, 8, and so on. This is used to slow down the counting rate of the timer. The timer block is configurable through APB or AHB-Lite register access.

Latest Resource Utilization details are available in the IP Core User Guide.

Features

  • Generates up to eight timers/counters that operate individually
  • Operates in either one-shot or continuous mode
  • Counts up or down
  • Register configuration through AMBA 3 APB Protocol v1.0 or AMBA 3 AHB-Lite Protocol v1.0

Block Diagram

Resource Utilization

No. of Timer Registers LUTs EBRs Target Device Synthesis Tools
4 462 754 0 CrossLink™-NX, Certus™-NX Synopsys® Synplify Pro®
4 446 600 0 Avant™-E Synopsys® Synplify Pro®

Order-Info

The Timer/Counter IP Core is provided at no additional cost with Lattice Propel Builder.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
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Timer/Counter IP User Guide
FPGA-IPUG-02139 1.4 12/20/2024 PDF 690.8 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Timer/Counter IP Release Notes
FPGA-RN-02022 1.0 12/20/2024 PDF 210.2 KB

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