Timer/Counter IP Core

Configurable with up to Eight Timers/Counters and Prescaler Block

The Lattice Semiconductor Timer/Counter IP can generate up to eight timers configured to operate individually. It consists of a prescaler block that counts the clock source and provides outputs of divided by 2, 4, 8, and so on. This is used to slow down the counting rate of the timer.

The design is implemented in Verilog. It can be configured and generated using Lattice Propel™ Builder. It is targeted for all devices and implemented using the Lattice Radiant™ and Lattice Diamond® software Place and Route tool integrated with the Synplify Pro® synthesis tool.

Tracks Timeouts - Timer/Counter IP is used to track timeouts in the system. It generates an interrupt to the CPU when a timeout is detected.

User-configurable for Software-controlled Start and Stop - the start and stop bits of control register are controllable through Advance Peripheral Bus (APB) or AHB-Lite register access.

Timer Register Write Accessibility - the period register is writable through Advance Peripheral Bus (APB) access and specified in the attribute Timer Preloaded Value.


  • Operates in either one-shot and continuous mode
  • Register configuration through AMBA 3 APB Protocol v1.0 or AMBA 3 AHB-Lite Protocol v1.0
  • Interrupt handling conforming to Lattice Interrupt Interface (LINTR) Standard
  • User-configurable preload and prescaler value access modes
  • Counts up or down

Block Diagram

Resource Utilization

No. of Timer Registers LUTs EBRs Target Device Synthesis Tools
4 462 754 0 CrossLink™-NX, Certus™-NX Synopsys® Synplify Pro®
4 446 600 0 Avant™-E Synopsys® Synplify Pro®


Quick Reference
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Timer/Counter IP Core – Lattice Propel Builder
FPGA-IPUG-02139 1.3 12/5/2023 PDF 818.2 KB

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