The Lattice Timer/Counter IP core can generate up to eight timers configured to operate individually. It consists of a prescaler block that counts the clock source and provides outputs divided by 2, 4, 8, and so on. This is used to slow down the counting rate of the timer. The timer block is configurable through APB or AHB-Lite register access.
Latest Resource Utilization details are available in the IP Core User Guide.